Faulty values being read on AD7091R-8

Hi,

We are stuck with the problem and unable to go forward with our design.

Could some one please look into the issue and help us?

Thank you,

Bharath

Hi Barathgopal,

      I am trying to understand how your set up works. From what I understand you are performing reset . Did you also perform power-on reset? This requires 66 pulses on the CONVST at 2us apart., then a software reset to reset the read only registers. Do you perform reset every conversion? I am asking this because the internal reference buffer requires 50ms to charge the 2.2uF decoupling cap. 

    What reading are you getting when 3 using 3 inputs? What is your sampling speed/throughput rate? If it s okay please share your timing of the digital signals so I can have a better understanding of the problem.

Regards,

Jonathan

Hi Jonathan,

I have connected the reset pin to VDD.I apply 66 CONVST pulses and perform software reset only at the start and I am using the default hardware configurations of AD7091R-8 EVAL. Inputs are connected at SL2, SL3, SL5 by removing the Buffers before those points.

We want to sample 3 channels at once (time between the channels should be <10 uS) and the sampling period is 250 Hz.

To test this, first I tried on single channel with 10 uS sampling period by connecting the i/p to gnd. My values read are 0x0001 and some times the values are 0x0EBD, 0x0EBE etc. I have not enabled the BUSY or alert bit.

I tried enabling 3 channels, and I can only read correct values on first channel. The other two channels are having wrong values but not every time. The spacing between each channel in this case is 10 uS.

SPI frequency is 8 MHz.

Thank you,

Bharath

Hi JonathanDSO.rar,
We are doing soft reset with CONVST pulse of 10 uS width as it is the smallest our MCU under test is able to generate.
The alert/busy pin when configured for busy (active low) is going low and returns high on applying low on CONVST pin.
With channel sequencer,  the sampling period for which we read correct values is 250uS. If we further reduce the period, the values read are wrong. But the conversion is completed according to busy pin.
With multiple channel write, we are able to reduce the sampling period down to 150 uS with correct conversion values.
The SPI clock supported by MCU is up to 8MHz and results are same with all the frequencies.

I have attached the screen shots of DSO. The SPI frequency used is 1MHz. All 3 channel inputs are always connected to gnd.
Please let me know if I need to do any other changes in Hardware or software to get the expected behavior.

Thank you,
Bharath

Hi Jonathan,

After making some code changes and carefully following the datasheet specifications, the observation is that, the spacing between 2 conversions should be more than 250uS for correct results.

The spi frequency doesn't have any effect on the conversion timing.

Why are we not able to achieve 1MSPS sampling rate?

What factors affect the sampling rate of the AD7091R-8?

Thank you,

Bharath

Hi Bharath,

    Let me dig some details into this and get back to you.

Regards,

Jonathan

Hi Bharath,

    Let me dig some details into this and get back to you.

Regards,

Jonathan

Hi Jonathan,

Thanks for your support.

We found that the issue is related to pulse width of CONVST. After achieving 500ns Pulse of CONVST, we are able to sample at every 1 uS interval.

Thank you,

Bharath