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AD7770 sampling progressing signals

Barbar
on Nov 11, 2018

Hello all.

I want to use the AD7770 to sample a precise point in input signal. I have 1 DAC that change the test signal for different level, and I do a single measure to each point.

There is no information on the AD7770 datasheet about the process of the sampling, like if there sample & hold and how much time it should be stable. If I use the SPI there is no direct wire I can start sampling just the SPI word for  SPI_SLAVE_MODE_ EN bit . But I see there is a SYNC_IN signal which can trigger the DRDY, but the data is not clear . Only Table 4 and Figure 4 put some information.  so all the start process is ambiguous . Because I do single measure for each point I need it to be stable, so my questions:

1. How much time before sending the SPI_SLAVE_MODE_ EN bit =1, the input must be stable?

2. Does the first measure with new input level is correct, or there is a need for several measures depend on the difference between levels I have at the input and capacitive stable time inside the ADC?

3. Can I use the SYNC_IN as trigger for the measure? And if so 

                 3a. What is the process, like first configure SPI_SLAVE_MODE_ EN bit. All that time hold SYNC_IN at "0" (measure disable) ,and the make it "1" .

                 3b. ANd even so there is a timing only for 16 kSPS, high resolution mode. and if I run at 2 kSPS, high resolution mode, does the delay make longer at the some ration?

Thanks

Bar.

 



Add some morte questions
[edited by: Barbar at 2:17 PM (GMT -5) on 12 Nov 2018]
  • 0
    •  Analog Employees 
    on Nov 18, 2018 1:13 PM over 2 years ago

    Hi Bar,

    AD7770 is a Sigma-Delta ADC, which conversion process is free-running with the master clock. It is continuously sampling - averaging N samples - providing data (DRDY pulse). There is no conversion start pin or so, like there would be on a SAR ADC.

    If you provide a SYNC_IN pulse, this will reset the digital filter, so it will take some time to settle and provide the first sample, the first DRDY. But keeping SYN_IN low does not disable the sampling process, it is the SYNC_IN rising edge what will reset the digital filter. See the red arrow below that shows the time between SYN_IN rising edge and the following DRDY. If your ODR is 2kSPS and High Resolution mode, it wil take 8331 MCLK cycles between the SYNC_IN rising edge and the DRDY pulse.

    SPI_SLAVE_MODE_EN is used to switch between DOUT interface, and SPI interface for reading back the ADC data. All the above applies to both cases. In SPI mode, aftwer a DRDY pulse the controller will be the master and will handle the data reading process. Otherwise, in DOUt interface, the AD7770 would be the master instead.

    Regards,

    Lluis.

  • 0 on Nov 18, 2018 4:16 PM over 2 years ago

    Thanks Lluis.

    So if I setting my enter level (I use DC levels ramp) and then place SYN_IN rising and wait for the DRDY. Can I be sure on the first DRDY I get correct data of the new level?

    This can be helpful for me not to waist two reading for each new level.

    Bar.

  • 0
    •  Analog Employees 
    on Nov 19, 2018 6:53 AM over 2 years ago in reply to Barbar

    Hi Bar,

    Generally the digital filter takes about three samples to settle. First sample is directly discarded, not shifted out (that's why there is a certain delay on first sample). Second sample (first DRDY) is 99% settled, and third sample (second DRDY) is fully settled.

    Regards,

    Lluis.