Data sheet says " A 105MHz external clock must be applied at the SCK pin to achieve 5Msps throughput. ". what should I do to use this ADC with different sampling rate , e.g. 3.125 Msps?
The minimum time between conversions is 200ns but in your application with 3.125Msps will require 320ns period. In this case you can increase either acquisition period or conversion period. If you choose to retain the conversion period to 171.5 ns you will still to use the 105MHz clock at SCK pin but increase the acquisition phase to 148.5 ns. The advantage of longer acquisition phase is the increase in the settling time for the DAC capacitor to charge. But you can also increase both acquisition period and conversion period to decrease the required clock for the SCK pin.
You can use 70MHz for SCK or 14.286nS SCK period. Total Conversion time will be 257.14nS with SCK Quiet Time from CNV and SCK Delay Time to CNV at 14.286nS and 28.571nS, respectively. Acquisition time will be 62.86nS. You can check the ADC timing characteristics table and timing diagram (Figure 21) of the datasheet. http://www.analog.com/media/en/technical-documentation/data-sheets/232314fb.pdf