The AD7357 data conversion process is initiated when CS goes low, this set the track and hold amplifier into hold mode. This samples the analog signal. at this point also the data bus is taken out of the three state which can now clock out the data IT requires 16 SCLK cycles to clock out this data. Once the data is complete the CS can now return high and the track and hold amplifier into its track mode. This routine is repeated whenever a conversion takes place. Using the maximum SCLK (80MHZ) and the 33ns acquisition time will maximize the sampling rate of the AD7357 at 4.2MSPS. ((1/80MHz) * 16) + 33ns) = 4.2MSPS.
Slowing the sampling rate would mean 2 things either slowing the SCLK and /or increasing the track or acquisition time. There is a minimum SCLK speed for AD7357, it is 500 kHz. This is the time clocking out the data. Longer tracking rate is a way advantage for the AD7357, this would give more time for the input sample to settle at its correct value. But the longer tracking will result to low throughput. The sampling rate would also depend on the frequency of the input signal. According to Nyquist theory at the sampling should be at lest twice the signal to be sampled.
Apologies for the late response, missed the thread. Anyway do you have plans using the AD7357 at minimum clock speed, what is the speed of the input signal?
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