Hi Gentleman, 

Could you please detail LTC2323-14 TDSCKCLKOUT spec?

Why we do only have a minimum value in the datasheet? is there a spec for Maximum Values or is it related to a variable timing depending on application that cannot be measured?


    •  Analog Employees 
    on Jun 29, 2018 9:44 PM over 2 years ago


    At present we do not have a maximum spec for this delay (TDSCKCLKOUT).  I would not expect it to exceed 5 nsec or so, but can you give me some more details about your concern?  Thanks.

  • Hello Doug, thanks for your feedback.

    We would like to be sure of the maximum delay time between the SCK falling edge and SDO Data Valid. It can be inferred from the LTC2323-14’s datasheet that this time is equal to t_DSCKCLKOUT + t_DCLKOUTSDOV. We have a maximum value for t_DCLKOUTSDOV (2 ns), however we only have the minimum value for t_DSCKCLKOUT (2.8 ns).
    On account of being an aeronautical project, we need to assure that our design works theoretically considering the device’s timing constraints, which includes determining when to sample new data bits. Therefore, knowing this timing information (t_DSCKCLKOUT max) would be desirable.
    In this application, to achieve a sampling rate of approximately 2 Msps , the generated SCK signal has a period close to 25 ns.

    Best Regards

    •  Analog Employees 
    on Jul 5, 2018 9:36 PM over 2 years ago

    Unfortunately we do not have a maximum spec for t_DSCKCLKOUT that we can publish or guarantee.  This part is intended so that CLKOUT provides the time base for capturing output data.  Doing this relieves the burden of having to know the delay from SCK to CLKOUT.  Typically an FPGA is used to receive the data, and it clocks SDO into registers based upon the edges of CLKOUT.

    I am not sure this is helpful, but let me know if there is anything else I can do to clarify.