Using AD7680 for ultra low sampling rate

Mohi,

Unfortunately I don't think the AD7680 can be used for such low throughput rates; you probably want to select a SAR ADC with an integrated conversion timer (doesn't use serial clock as clock source) or a Sigma Delta Converter.   The selection will be dependent upon a number of factors in terms of power, cost, solution size, resolution, etc.  Can you tell me a bit more about your application so that we can assist you in selecting the best product for your problem statement? 

Regards,

Sean

Hi Sean,

Thanks for your quick reply. Here is the scenario.

ADA4350 (TIA) is connected to a photo diode. The same TIA will connect to a ADC (the one being searched).

The resolution requirement is 14 or 16 bits - later is preferred.

Signal level from TIA can be as low as a couple of mV - the higher end of the signal can be adapted to the ADC's allowable range. It will be single ended and single channel.

We are suspecting 10 to 100 Hz will be sufficient sampling rate. In any event, the rate will not go beyond 1kSPS.

Power and cost is not a concern.

I hope to have answered all your questions. Please let me know if anything is missing. 

Mohi

Mohi

1) The behavior of CNV will be dependent on the chosen interface mode.   They are too numerous to explain here but read through the datasheet sections on the interface configurations and they are fairly well explained there. 

2) Yes the uC has full control of the start of conversion.  However once a conversion is initiated there is no way to terminate it and you must wait a minimum tcycle time of 2us to initiate another conversion.

3)  That is correct.   The AD4000 architecture allows the sampling capacitor to be reconnected to the input prior to the end of conversion.  This will not always be the case but for this part it is true. 

I took a quick look at your schematic and was your intention to place -40V on the cathode of the diode or was this meant to be 40V such that the PD is reverse biased?   

Also if I can suggest a design tool we do have a photodiode wizard (see link below) that will help you optimize the ADA4350 in your application

https://tools.analog.com/en/photodiode/

Sean

Thanks Sean. You were very helpful in selecting the right component for our purpose. I am will be using AD4000.

The intention was to show that PD is reverse biased. I have been using LTSpice to simulate and select the right gain resistor+capacitor combinations and it does help a lot. But I will consult the URL you suggested.

Thanks again for all your help!

Hi Sean,

Is there a multichannel version of  AD4000 and 7685?

Also, What ADC in AD's offerings considered dual slope? 

Thanks,

Mohi,

There are multichannel versions but they are multiplexed. 

AD4000  ->  AD4696 (16-Channels )  8-Channel versions later this year.

AD7685  ->  AD7689/99/82,  8 Channels (250KSPS, 500KSPS), 4 Channels (82)

I will double check but I don't believe we offer any dual-slope ADCs in our current portfolio.  What is driving the inquiry?  Is it that you have a specific DC accuracy and robustness requirement? If yes, what are the commercial prospects for this design in terms of annual volume, etc?  

Based on your response I may have a member of my team reach out to you directly about other options.  

Hi Sean,

Since the input is multiplexed, it means each Conversion + acquisition will be offset in time?

Any version with simultaneous sampling?

The reason I was thinking about the dual-slope version is to be cost effective. What I am reading is these are very slow and each conversion can take up time in milliseconds. Correct?

Even though our signal is slow, but not to DC level. So dual-slope might not be a good fit. Thinking out loud.

Thanks,

Mohi,

To avoid making this process longer than it needs to be can you tell me the following please?

1)  How many channels you need?

2) The approximate dynamic range you need, i.e. how many decades of signal amplitude swing you are likely to see and need to resolve.

3) The measurement resolution and accuracy you need. 

4) An approximate estimate of the cost per channel?

I'm sure we can help you find something that will work for the price point you are looking to hit.   Just to confirm you must absolutely have control over the sampling instant and thus cannot consider a continuously sampling architecture such as sigma delta correct?

Sean

1) 12 channels

2) The input swing from the photodiode is expected to be from few nA to few mA; hence the reason to select ADA4350 with built-in switch. The output of ADA4350 is from 0 to 4V if 5V supply volt is used.

3) For each cycle in 100Hz sampling frequency, <±100uV is desirable.

4) Performance is more important, and cost usually does not matter but always a concern. I will leave it out for now.

Yes. The sampling rate has to be low, and the instance must be controlled.

Thanks,

Mohi,

I would have a look at a combination of LTC2358-16 (8 Channels) and LTC2357-16(4 channels) from a performance perspective (using SoftSpan 1) and then adding digital oversampling to get the SNR into the 90+dB range for your signal.  The drawback is you're going to need to generate bipolar supply rails (-4 to 9V) for the headroom.

Alternatively take a look at 2x AD7606-6. This solution will run off a single 5V supply and has some native oversampling but it doesn't have the unipolar mode.   Thus you may need to pull some tricks with the input to convert the unipolar output of the ADA4350 into a Bipolar swing to gain back closer to the full range.

Either way there really isn't an ideal solution from a simultaneous sampling perspective.

What I might suggest is that if you went with a single AD4696 that running at 1MHZ you would effectively have 12us between Channel 0 and Channel 11's sampling instance.  Is that type of delay going to impact your measurement or could you live with doing bursts of N*12 channels at a periodic rate of 100-10KSPS?  Then I think you avoid all the challenges on the simultaneous sampling solutions.

Sean 

Thank you Sean for all the suggestions.

I get back to you after tomorrow's meeting and will let you know which direction we are heading.

Mohi

Hi Sean,

The decision is to use AD4000 to future proof the design and also to avoid the long cable run of analog signal to a centralized processing unit.

One question about the power consumption of AD4000. It is 1.8V device; however, the current consumption is not mentioned anywhere in the DS (or I am not looking hard enough). On page 6 of datasheet, power dissipation numbers are given for different sampling rates. Can one assume this to be power consumption (vs power dissipation) numbers also?

Since AD4000 is connected to ADA4350 on one side and uC on the other, is ADP7118AU still a good choice - I am looking at UG-1042.pdf.

If Vref and V_Drv share the same 3.3V rail as the uC, do you see issues here?

Does Vref has to be buffered as done in UG-1042?

Thanks,

Hi Sean,

The decision is to use AD4000 to future proof the design and also to avoid the long cable run of analog signal to a centralized processing unit.

One question about the power consumption of AD4000. It is 1.8V device; however, the current consumption is not mentioned anywhere in the DS (or I am not looking hard enough). On page 6 of datasheet, power dissipation numbers are given for different sampling rates. Can one assume this to be power consumption (vs power dissipation) numbers also?

Since AD4000 is connected to ADA4350 on one side and uC on the other, is ADP7118AU still a good choice - I am looking at UG-1042.pdf.

If Vref and V_Drv share the same 3.3V rail as the uC, do you see issues here?

Does Vref has to be buffered as done in UG-1042?

Thanks,