Using AD7680 for ultra low sampling rate

Mohi,

Unfortunately I don't think the AD7680 can be used for such low throughput rates; you probably want to select a SAR ADC with an integrated conversion timer (doesn't use serial clock as clock source) or a Sigma Delta Converter.   The selection will be dependent upon a number of factors in terms of power, cost, solution size, resolution, etc.  Can you tell me a bit more about your application so that we can assist you in selecting the best product for your problem statement? 

Regards,

Sean

Hi Sean,

Thanks for your quick reply. Here is the scenario.

ADA4350 (TIA) is connected to a photo diode. The same TIA will connect to a ADC (the one being searched).

The resolution requirement is 14 or 16 bits - later is preferred.

Signal level from TIA can be as low as a couple of mV - the higher end of the signal can be adapted to the ADC's allowable range. It will be single ended and single channel.

We are suspecting 10 to 100 Hz will be sufficient sampling rate. In any event, the rate will not go beyond 1kSPS.

Power and cost is not a concern.

I hope to have answered all your questions. Please let me know if anything is missing. 

Mohi

Mohi,

I would suggest taking a look at the AD7685 or the AD4008.  Both have significantly higher maximum throughput than you need but should be able to operate in the range of sample rates you are interested in.  The advantage of the AD4008 is the HI-Z mode that significantly reduces and linearizes the charge kick-back from the ADC which will result in less output transients at the output of your amplifier whereas the AD7685 will be a bit simpler to get up and running as their is no configuration to be done.  Both are pin compatible and offered in 10-ld LFCSP.

If you prefer leaded packages the MSOP-10 is available in both product families by selecting the AD4004 over the AD4008.

Hope that helps

Sean

Sean - I appreciate your quick responses.

To avoid any mishap on my side, I am including an example of the expected signal that will be sampled.

The signal is slow but also non synchronized to any event. The sampling has to be performed continuously but at a very slow rate. 

I have not gone through the datasheets, so I am hoping you can help me if the suggested parts are suitable for this purpose. Few questions about AD4008.

1. How fast does the ADC_CLK run?

2. The conversion time is 1.79 uSec. Correct?

3. Will it run in either continuous or single sample mode?

4. It can be used for single-ended, positive volt only signal

-Mohi

Mohi,

1.)  The internal ADC Clock runs fast enough that a single conversion is completed in the conversion time of 270-320ns.   

2)  You can repeat a conversion every 2us but the period can be as long as you like.  The 1.79us you reference is the minimum acquisition time, that is the time for the ADC to acquire the input signal before the next conversion start pulse is issued.  It only takes 270 - 320ns for the device to produce a result and then you can read he data out during the next acquisition period over the serial interface.

3) Yes you can execute any number of conversions at any time assuming you are not changing the configuration (AD4008 only).  In that case you must execute a minimum number of conversions to load the desired configuration before proceeding with your sampling.

4)  Correct.   The output is unipolar from 0 to VREF.

Can you provide an example for how you intent to hook-up and test your TIA.   I'm a bit confused by the waveform you've provided.   I'm pretty sure it will work as you've drawn I would just like to be sure.

Sean

Hi Sean,

From previous work, the waveform is established to look similar to what I had drawn earlier. The sudo schematic shows the connections in the linked image.

https://drive.google.com/file/d/1Rt_wiVQQO88kDQ4L-HxUkmICMye_JuQK/view?usp=sharing

I am leaning to use AD4000 to future proof the design because of its higher SPS. Please suggest any modification to my conceptual schematic.

I need to ask you few questions for my understanding of ADC operation and for later use of it.

1. In Figure 50, CNV signal is shown in ORd configuration. Does this mean it can go high-low-high OR stay high for the entire conversion time? 

2. Does this mean uC is controlling the conversion time?

3. The t(cyc) = t(conv) + t(acq) - small overlap. Correct?

Thanks,

Mohi

1) The behavior of CNV will be dependent on the chosen interface mode.   They are too numerous to explain here but read through the datasheet sections on the interface configurations and they are fairly well explained there. 

2) Yes the uC has full control of the start of conversion.  However once a conversion is initiated there is no way to terminate it and you must wait a minimum tcycle time of 2us to initiate another conversion.

3)  That is correct.   The AD4000 architecture allows the sampling capacitor to be reconnected to the input prior to the end of conversion.  This will not always be the case but for this part it is true. 

I took a quick look at your schematic and was your intention to place -40V on the cathode of the diode or was this meant to be 40V such that the PD is reverse biased?   

Also if I can suggest a design tool we do have a photodiode wizard (see link below) that will help you optimize the ADA4350 in your application

https://tools.analog.com/en/photodiode/

Sean

Thanks Sean. You were very helpful in selecting the right component for our purpose. I am will be using AD4000.

The intention was to show that PD is reverse biased. I have been using LTSpice to simulate and select the right gain resistor+capacitor combinations and it does help a lot. But I will consult the URL you suggested.

Thanks again for all your help!

Hi Sean,

Is there a multichannel version of  AD4000 and 7685?

Also, What ADC in AD's offerings considered dual slope? 

Thanks,

Mohi,

There are multichannel versions but they are multiplexed. 

AD4000  ->  AD4696 (16-Channels )  8-Channel versions later this year.

AD7685  ->  AD7689/99/82,  8 Channels (250KSPS, 500KSPS), 4 Channels (82)

I will double check but I don't believe we offer any dual-slope ADCs in our current portfolio.  What is driving the inquiry?  Is it that you have a specific DC accuracy and robustness requirement? If yes, what are the commercial prospects for this design in terms of annual volume, etc?  

Based on your response I may have a member of my team reach out to you directly about other options.