AD7716: FAQ

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  • AD7716: Relationship between SCLK, FCLKIN and resolution

    Question I am facing a 89c52 to master the ADC7716 . 1.The sclock is abut 3MHz (the max I can give him) 2. cut – off : 73Hz 3. input : regular E.C.G signal ? in slave mode : is a FCLKIN needed ?…
  • AD7716: slave mode

    Question I am confused which signals will start the transfer, CASCIN and SCLK or RFS and SCLK?The data will be sent out when which signal is turned low, RFS or DRDY? Answer In Slave Mode, the data will…

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