Introduction

The AD4112 features a low noise, fast settling, 24-bit, Sigma-Delta (Σ-Δ) analog-to-digital converter (ADC) with a built-in analog front end (AFE) designed for measurements of fully differential or single-ended bipolar voltage inputs (±10 V) with high impedance (≥1 MΩ), as well as current inputs from 0 mA to 20 mA. It includes an internal multiplexer with 16 configurable channels, allowing flexible support for either voltage or current inputs. It supports a maximum channel scan rate of 6.21 kSPS (161 µs) while delivering fully settled data. The integrated digital filter offers flexible configuration options, allowing users to choose from various filter settings based on the specific requirements of each application channel. This makes the AD4112 well-suited for industrial automation systems, including programmable logic controllers (PLCs), distributed control system (DCS) modules and other Instrumentation measurements.

Scope

This AD4112 LTspice model focuses solely on one channel of the AD4112, disregarding all other channels, functions, and pins. Figure 1 shows the AD4112 model, which can be configured by adjusting various parameters. These parameters work similarly to how the actual part is being configured through its register settings. Only the essential parameters for simulating the ADC output are included. The model supports transient analysis and AC analysis. In transient analysis it allows the user to simulate an ideal and real-world situation on how the ADC output is affected, specifically the settling time in response to a step change in the input for different configurations. AC analysis shows the frequency response of the digital filter and when an additional front-end circuit is added.

Figure 1. AD4112 Model Symbol

This document serves as a guide in using the AD4112 model and should be used alongside the AD4112 datasheet for a comprehensive understanding of the simulation results. This document will discuss the model’s different pin functions, parameters, and example demo circuits.

Pin Description

The AD4112 model does not include all the pins available in the actual part. The only pins included in the model are those essential for simulating the output of the AD4112. Table 1 shows the different pins, their type, description, and allowable range.

Table 1.

Pin Name	Type	Description	Range
VIN0 & VIN1	Input	Analog input pins for signals. Differential Input voltage range (VIN0-VIN1) Specified: -10V to +10V Functional: -Vref*10 to +Vref*10	For AVDD ≥ 4.75V: -20V to +20V For AVDD ≥ 3V: -12V to +12V
VINCOM	Input	Voltage Input Common. Voltage inputs are referenced to this pin when configured as single-ended. Connect this pin to analog ground.	GND or 0V
IIN0+	Input	Current input 0.	-0.5 mA to 24 mA
IIN0-	Input	Current input return 0. Connect this pin to the analog ground	GND or 0V
REF+	Input	External Reference Input Positive Terminal	AVDD to AVSS + 1V
REF-	Input	External Reference Input Negative Terminal	AVSS to AVDD – 1V
REFOUT	Output	Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Decouple this pin to AVSS using a 0.1 µF capacitor.	~2.5V
AVDD	Input	Analog Supply Voltage.	3.0V to 5.5V with respect to AVSS
AVSS	Input	Negative Analog Supply.	-2.75V to 0V, nominally set to 0V
VBIAS-	Input	Voltage Bias Negative. The pin is setting bias voltage for the voltage input analog front-end. Connect this pin to AVSS.	VBIAS- = AVSS
IOVDD	Input	Digital I/O Supply.	2V to 6.35V with respect to AVSS
CLK	N/A	This pin is currently unused because the internal clock of the ADC is being used. Connect this pin to GND.	2 MHz ± 2.5% (internal clock of the ADC)
Vout	Output	This is the output pin of the ADC. The model requires a load resistor to GND with a value 10 MΩ.	For Voltage input: Vout = (VIN0 – VIN1)/10 For Current input: Vout = IIN0+ * 50
GND	N/A	Connect this pin to GND.

Accessing the model

To access the AD4112 model, first download the latest version of LTspice from this link. After installing LTspice, the user should be able to create a schematic and choose the AD4112 from the components. To find the AD4112 model, navigate to Component > ADC and look for the AD4112 symbol. Upon adding the AD4112 symbol, the user may right-click on the symbol. A window should appear that will allow the user to configure the parameters, and a button to open an example circuit. The user may access the example circuit for reference and begin creating their schematic.

Quick Start Guide

Figure 2. Open Example Circuit

Use the following procedure to perform a quick measurement using the example circuit.

1. Open the example circuit. See Figure 2
2. Click the ‘Run/Pause’ button. (Highlighted as #1 in Figure 3)
3. To measure the output, click on the ‘Vout’ node. (Highlighted as #2 in Figure 3)
4. To measure the differential input, click ‘VIN0’ and drag the mouse to ‘VIN1’. (Highlighted as #3 in Figure 3)
5. To add another plot pane, right click on the plot and click ‘Add Plot Pane’. (Highlighted as #4 in Figure 3)
6. Right click on ‘V(vout)’ on the plot pane to add the ‘*10’ factor due to the internal AFE division ratio of 10 for voltage inputs only.
7. Click on the voltages on the plot pane to measure the voltage level and time.

Figure 3. Example Circuit Quick Guide

Parameter Description

Figure 4. AD4112 Parameter

The AD4112 model includes several parameters. These parameters allow the model to be configured to different settings, such as configuring the selected input (Voltage or current input), reference selection, ODR, filter type, etc. You may access the parameters by right-clicking on the model symbol and setting the configurations as shown in Figure 4. Table 2 shows the allowable values for each parameter and its functions.

Table 2.

Parameters	Range	Description
ODR	1.25 to 31250	This parameter selects the output data rate to be used. Refer to the datasheet for the available ODRs for Sinc3 and Sinc5+Sinc1 filter.
fsrSEL	0/1/2/3/4	This parameter sets the Full Scale range. fsrSEL = 0: ±10 * Vref fsrSEL = 1: ±10V fsrSEL = 2: ±5V fsrSEL = 3: 0V to 10V fsrSEL = 4: 0V to 5V
inputSEL	0/1/2/3	This parameter selects the analog inputs. Note that only one channel is used for analysis. inputSEL = 0: Sets VIN0-VIN1 (differential input) inputSEL = 1: Sets VIN0-VINCOM (single-ended input) inputSEL = 2: Sets VIN1-VINCOM (single-ended input) inputSEL = 3: Sets current input IIN0+ and IIN0-
sincSEL	0/1	This parameter selects the filter type to be used. sincSEL = 0: Sinc3 filter sincSEL = 1: Sinc5+Sinc1 filter
clkSEL	0	This parameter sets the internal clock to be used. clkSEL = 0: Internal 2 MHz clock
refSEL	0/1/2	This parameter sets the reference to be used. refSEL = 0: When an external reference is being used (REF+ - REF-) refSEL = 1: When internal reference 2.5V is being used refSEL = 2: Sets AVDD-AVSS
sing_cyc	0/1	This parameter enables/disables the single cycle mode sing_cyc = 0: Single cycle mode is disabled sing_cyc = 1: Single cycle mode is enabled

Demo Circuit Analysis

LTspice supports various types of simulations and analysis; however, for the AD4112 model, only transient and AC analyses are available.

Transient Analysis

The AD4112 model emulates the ADC output using the transient analysis in LTSpice. It models the step response of the output of the ADC and calculates the associated settling time (Tsettle) using different filter types, ODR, and single-cycle mode. If there were a step change on the analog input, it takes the full settling time (Tsettle) of the digital filter until a valid conversion is achieved. The step response assumes that the ADC is continuously converting on a single channel.

To properly simulate the transient analysis of the model, a startup delay of at least Tsettle is required for the input voltage. To simulate startup behaviour, please consider the simulation startup command.

For example, ".tran 0 5m startup". For slower ODRs, longer simulation time may be required.

If startup is present, then DC sources will start at 0V and reach their final value 20 µs later. For other ramp rates, please use piecewise linear (PWL) or pulse sources.

For lower ODRs, the simulation time may be lengthy before the output fully settles. In such cases, the AFM integrated available in the AD411x ACE plugin may be used as an alternative simulation tool to determine the settling time and step response

Simulation with voltage input mode

In this demo, we will simulate the step response of the AD4112 output when a voltage input step-change is applied, whether synchronous or asynchronous to the start of conversion. The term synchronous means that the voltage input step change has occurred at the same time as the ADC's start of conversion. This scenario is ideal, but in practical applications, it's rare to apply an input step-change exactly at the beginning of the ADC conversion, which is why it's referred to as asynchronous.

Note: For voltage inputs, the voltage divider on the analog front end has a division ratio of 10 that enables an input range of ±20 V from a single 5 V power supply. To get the actual voltage output, Vout must be multiplied by a factor of 10, as shown in Figure 6.

Ex. 1: Sinc3 Filter with a synchronous input

The voltage input, V3 = PULSE (0 2.5 97u 1n 1n 10m), which includes a delay of 97 microseconds, is applied to the ADC input, see Figure 5. This delay matches the settling time. This delay matches the settling time of the Sinc3 filter at the programmed output data rate (ODR) of 31250 samples per second (SPS), synchronizing the input step change with the start of the ADC conversion. The Sinc3 filter's settling time is approximately equal to 3/ODR. When a synchronous voltage input step change occurs, the Sinc3 filter's output fully settles by the third ODR cycle, as illustrated in in Figure 6.

Figure 5. Demo Circuit: Synchronous input step change using Sinc3 Filter

Parameter configuration:

ODR = 31250 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 0: VIN0-VIN1 (differential input)
sincSEL = 0: Sinc3 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference
sing_cyc = 0: Single cycle mode disabled

Figure 6. Step Response: Synchronous input step change using Sinc3 Filter, Single Cycle Disabled

Ex. 2: Sinc3 Filter with an asynchronous input

In a practical user scenario, it is challenging to apply an external input step change synchronously with the ADC's start of conversion. Typically, the input step change occurs asynchronously. Figure 7 illustrates how to simulate transient analysis for voltage inputs using the Sinc3 filter when the input step change is asynchronous to the ADC's start of conversion. The voltage input, V3 = PULSE (0 2.5 122u 1n 1n 10m), includes a delay of 122 microseconds, which exceeds the approximate settling time of the Sinc3 filter at an ODR of 31250 SPS. This delay indicates that the input step change occurs while the ADC is in the process of conversion.

Figure 7. Demo Circuit: Asynchronous input step change using Sinc3 Filter

Parameter configuration:

ODR = 31250 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 0: VIN0-VIN1 (differential input)
sincSEL = 0: Sinc3 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference

When asynchronous analog input step change occurs with single cycle settling mode disabled (sing_cyc = 0), and the Sinc3 filter is used, the analog input does not settle until the 4^th ODR period, since it requires at least three conversion cycles after the step change for the output to reach the final settled value, as shown in Figure 8.

Figure 8. Step Response: Asynchronous input step change using Sinc3 Filter, Single Cycle Disabled

Figure 9 shows the same step on the analog input but with single cycle settling enabled (sing_cyc = 1). This mode reduced the output data rate to be equal to the settling time of the selected output data rate, thus, the output reaches the settled value after at least a single conversion cycle. Note that this mode has no effect with the sinc5 + sinc1 filter at output data rates of 2.6 kSPS and less or when multiple channels are enabled. This can be explained in the next set of examples.

Figure 9. Step Response: Asynchronous input step change using Sinc3 Filter, Single Cycle Enable

Ex. 3: Sinc5+Sinc1 Filter with a synchronous input

The voltage input, V3 = PULSE (0 2.5 161u 1n 1n 10m), which includes a delay of 161 microseconds corresponding to the settling time of the Sinc5+Sinc1 filter at a programmed output data rate (ODR) of 31250 samples per second (SPS), is used to synchronize the step change with the start of the conversion, see Figure 10.

Figure 10. Demo Circuit: Synchronous input step change using Sinc5+Sinc1 Filter

Parameter configuration:

ODR = 31250 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 0: VIN0-VIN1 (differential input)
sincSEL = 1: Sinc5 + Sinc1 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference
sing_cyc = 0: Single cycle mode disabled

Referring to the plot in Figure 12, the output reaches its final settled value after 5 conversion cycles (5/ODR). Note that for Sinc5+ Sinc1, the number of conversion cycles to achieve a fully settled value varies across different ODRs due to its cascaded filter stages, as shown in Figure 11.

Figure 11. AD4112 Digital Filter Block

The Sinc5+Sinc1 filter is a Sinc5 filter followed by an averaging block (sinc1). The Sinc5 block has a fixed maximum output data rate of 31250 SPS, and the sinc1 block output data rate can be varied to control the final ADC output data rate. The amount of averaging per selected output data rate can be seen in the constants tab of AD4112 Digital Filter Model and the final settling time can be calculated as follows:

[Please visit the site to access the math equation]

In this example, the averaging block (Sinc1) is bypassed (AVG = 1), thus, the settling time is approximately equal to 5/ODR or 322/MCLK as shown in Figure 12.

Figure 12. Step Response: Synchronous input step change using Sinc5+Sinc1 Filter, Single Cycle disabled

Ex. 4: Sinc5+Sinc1 Filter with an asynchronous input

Like the Sinc3 filter, the Sinc5+Sinc1 filter requires a full settling time following an asynchronous step change in the analog input for the output to reach its final steady-state value. The difference between the two is that in Sinc3 filter, the settling time is always approximately 3/ODR, while in Sinc5+Sinc1 the settling time depends on the amount of averaging per selected output data rate, as discussed previously. Another difference between the two filter configurations is the effect of the Single Cycle Mode. Note that this mode has no effect with the sinc5 + sinc1 filter at output data rates of 2600 SPS and less.  

Figure 13 illustrates a voltage input, V3 = PULSE (0 2.5 580u 1n 1n 10m), which includes a delay of 580 microseconds, which exceeds the approximate settling time of the Sinc5+Sinc1 filter at an ODR of 2597.4 SPS. This delay indicates that the input step change occurs while the ADC is in the process of conversion.

Figure 13. Demo Circuit: Asynchronous input step change using Sinc5+Sinc1 Filter

Parameter configuration:

ODR = 2597.4 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 0: VIN0-VIN1 (differential input)
sincSEL = 1: Sinc5 + Sinc1 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference

When an asynchronous analog input step change occurs with single cycle settling mode disabled (sing_cyc=0), the output reaches the settled value after at least a single conversion cycle, as shown in Figure 14. When you enable the single cycle settling mode (sing_cyc=1) you will notice that the output will remain the same. The sing_cyc mode allows the output data rate to be equal to the (1/settling time), and this can be automatically achieved in Sinc5+Sinc1 filter at ODR<2600SPS; therefore, the sing_cyc mode has no effect on the output data rate.

Figure 14. Step Response: Synchronous input step change using Sinc5+Sinc1 Filter, ODR<2600 SPS

Simulation with current input mode

The AD4112 model also incorporates an internal 50Ω shunt resistor to condition the signal to a voltage level suitable for the ADC. In this configuration, the IIN pins can be used as illustrated in Figure 15.

Figure 15. Demo Circuit: Asynchronous input step change using Sinc3 Filter

Parameter Configuration:

ODR = 31250 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 3: IIN0+ and IIN0-
sincSEL = 0: Sinc3 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference
sing_cyc = 0: Single cycle mode disabled

The output voltage for a current is equal to IIN0*50 Ω. With 5mA input current, the output voltage of the model is ~250 mV. The output step response is very similar to the previous voltage input example, as shown in Figure 16.

Figure 16. Step Response: Asynchronous input step change using Sinc3 Filter, Single Cycle Disabled

AC Analysis

The AD4112 model is capable of simulating and analyzing the frequency response of the Sinc filters using LTspice’s AC analysis feature. By leveraging this model, users can visualize the Sinc filter’s behaviour across different frequencies of the set ODR, helping to optimize performance and ensure signal integrity in precision measurement applications.

LTspice’s AC analysis works by performing a small-signal frequency sweep on a circuit to determine how it responds to different frequency inputs. The users can define the frequency range and the number of points per sweep, allowing for detailed examination of signal attenuation and amplification. This method is particularly useful for evaluating filter designs, stability, and frequency-dependent characteristics in circuits like the Sinc filters of the AD4112 model.

To perform AC analysis, a small signal is applied to the voltage/current input by right-clicking on the voltage source to open its properties. In the dialog box, set the ‘AC Amplitude’ to 1 as shown in Figure 17. With this setup, it ensures that the voltage provides an AC signal for analysis across the set frequency range.

Figure 17. Small Signal AC input

The next step is to configure the AC analysis parameters, see Figure 18. Choose the type of sweep, Decade is ideal for visualizing the frequency response across a wide range of frequencies. The number of points per decade determines the number of points the LTSpice evaluates. Increasing this value produces smoother plots with greater resolution. The start and stop frequency define the range of frequencies to be covered for analysis. The user may consider using the command “.ac dec 1000 0.1 10Meg” as an example for AC analysis. Note that for AC analysis, the *10 factor on Vout plot is not required.

Figure 18. AC Analysis parameters

This section will demonstrate how to utilize the AD4112 LTSpice model for AC analysis and investigate the frequency response of Sinc3 and Sinc5 + Sinc1 filters through different examples. See Figure 19 for example circuit configuration. These simulations can be used alongside the AD4112 Digital Filter for a better understanding of the results.

Figure 19. Demo Circuit: Digital Filter Frequency Response Analysis

Simulation of Digital Filter Frequency Response

The following examples will help visualize how the filter behaves by applying a small signal in a voltage or current input mode. These will demonstrate the -3dB frequency and the notches formed by the Sinc3 and Sinc5+Sinc1 filter based on the configured ODR. Deep notches, accompanied by the attenuation of signals within the notch, emerge at both the output data rate and its integer multiples. The position of notches is the same for each filter order. However, notch width increases as filter order increases. A higher order filter also has a steeper roll-off which corresponds to a lower -3dB frequency and a higher stopband attenuation.

Ex. 1: Sinc5+Sinc1 Filter at ODR = 31250 SPS

The filter basically has notches at the output data and multiples of the data rate, and you'll see that the -3 dB frequency at somewhere around 0.2 times the output data rate and then this rolls off sharply under an envelope of 100dB per decade so there is a notch at the output data rate which is 31250 SPS and multiples of it.

Parameter Configuration:

ODR = 31250 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 0: VIN0-VIN1 (differential input)
sincSEL = 1: Sinc5+Sinc1 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference

As discussed previously, the Sinc5 block has a fixed maximum output data rate of 31250 SPS and the Sinc1 block output data rate can be varied to control the final ADC output data rate through averaging. The number of averaging changes the -3dB point, optimizing the noise, settling time, and rejection, which is ideal for multiplexed systems.

Figure 20. Frequency Response: Sinc5+Sinc1 Filter at ODR = 31250 SPS

Ex. 2: Sinc3 Filter at ODR = 31250 SPS

Figure 21 shows the frequency domain filter response for the Sinc3 filter. The filter basically has notches at 31250 SPS and multiples of it, and you'll see that the -3 dB frequency is at ~9.43kHz, and its envelope of attenuation is increasing at a rate of 60dB per decade.

Parameter Configuration:

ODR = 31250 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 0: VIN0-VIN1 (differential input)
sincSEL = 0: Sinc3 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference

If you compare it to Sinc5+Sinc1 example above, you’ll see that Sinc5+Sinc1 has steeper roll-off and lower -3dB frequency at this speed. This indicates that Sinc5+Sinc1 is best at higher speed. However, at lower ODRs, Sinc3 offers the best noise performance as it has good roll off over frequency and wide notches for good rejection over frequency vs Sinc5+Sinc1. Therefore, Sinc3 filter is the best choice for single channel noise performance at lower data rates.

Figure 21. Frequency Response: Sinc3 Filter at ODR = 31250 SPS

Simulation with External Anti-Alias filter (AAF)

Sinc filter's frequency response is reflected around the modulator frequency (FMOD), consequently, it offers 0dB attenuation at frequencies that are integer multiples of the modulator frequency. Therefore, an anti-alias filter in the analog domain is required to adequately attenuate these frequencies.

AD4112 is a sigma-delta converter, therefore, it does not require a complex anti-alias filter due to its oversampling of the analog input. Typically, a single pole (perhaps a two-pole) RC filter is sufficient for the anti-alias filter. An example of an anti-alias filter is shown in Figure 22. For the AD4112 the recommended anti-aliasing is 4.7nF/180Ω, as this combination will give you the optimum performance and was used in the EMC evaluation.

Figure 22. Demo Circuit: AC analysis with External RC Anti-Alias filter

Parameter Configuration:

ODR = 31250 SPS
fsrSEL = 0: ±10 * Vref
inputSEL = 0: VIN0-VIN1 (differential input)
sincSEL = 0: Sinc3 filter
clkSEL = 0: internal 2 MHz clock
refSEL = 1: internal 2.5V reference
sing_cyc = 0: Single cycle mode enabled

The frequency plot in Figure 23, the red plot represents the anti-alias filter’s frequency response, while the blue plot represents the frequency response of the output, which is a combination of the frequency response of the Sinc3 filter and anti-alias filter. Note that in practical applications, the digital filter must set the overall signal bandwidth, as this would reduce the ADC noise. Despite having a slow roll-off of the external anti-alias filter, this should be sufficient so that any noise around sampling frequency and its multiples is attenuated and would have a minimal influence on the total RMS noise_. Another thing to note here is that this model only modeled the digital filter response, the modulator response on the actual AD4112 design would have good attenuation around FMOD, thus the main frequency to consider for anti-aliasing is 2*FMOD.

Figure 23. Sinc 3 Filter Frequency Response with External RC Anti-Alias filter

Revision History

6/2025 – Revision 0: Initial version