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About AD9122 can not be locked

xwfpga — Fri, 16 Sep 2022 06:34:15 GMT

您好工程师：

当我使用AD9122时，内部锁相环无法完成锁定，参考时钟来自AD9518产生的500MHz时钟，频率倍增产生1GHZ DACCLK

配置如下

0B 20

0C E1

0D D4

0A 电容

0A A0

最后读到0E的7位不能是1，不能完成锁定，希望能帮忙解决，谢谢！

LTC2495IUHF#PBF

RamyaRaviCapgemini — Fri, 26 Aug 2022 12:33:29 GMT

Could you please review the schematics of LTC2495IUHF#PBF

Review: AD7328, AMP04 and AD5734

athuljith — Tue, 23 Aug 2022 05:18:07 GMT

Hi,

I am using AD7328, AMP04 and AD5734 in design for the data conversion applications. Could you p[lease review the attached schematic and let me know if any issue is found. These are used for processing analog signals of +-15V under 500KHz.

Regards

Athuljith R

ADM3251E power consumptin @ 3.3V

israelblanco — Fri, 19 Aug 2022 16:20:32 GMT

Hi,

I'm not quite sure if the current consumtion while powering the ADM3251E at 3.3V is just = 2.5 + 12 + 6.2 = 20.7 mA like the datasheet seems to display. The concerns comes from comparing it to the consumption when it is powered up with 5V. I know the internal DC-DC is not enbled on the fist case but still, it's such a big difference in consumption comparing powering it up with 5V or with 3.3V.

Can some one please give me a hint?

Thank you very much.

High-speed ADC and DAC

AbhijeetG — Wed, 01 Jun 2022 14:14:48 GMT

I am new to designing ADC and DAC circuits. I have attached schematics containing ADC (AD9208), DAC(AD9172), and clock synthesizer (HMC7044). Please review the front-end design of ADC and the Output of DAC sections. I have mentioned the frequency of operation for ADC and DAC. Let me know if I am missing something or if anything has to be modified. Thanks for your help.

Regards,

Abhijeet

AD1674BRZ Datasheet last revision

JinA — Sat, 14 May 2022 09:07:47 GMT

AD1674BRZ，好像和Datasheet REV C有区别。
REF OUT 值为 2.5V，而在数据表中为 10V。
是新产品的新设计还是定制的？

AD7949 replacing bye AD7689

Flotho — Tue, 19 Apr 2022 12:55:36 GMT

Hello,

is it possible to replace the AD7949 bye the AD7689 without changing the software? How does the SPI output looks like?

I hope you can share more infomation or links.

BR Florian

AD7124-4 IOVDD和AVDD

hehe — Mon, 21 Mar 2022 07:29:42 GMT

Hi,

Due to IOVDD relative to DGDD,AVDD relative to AVSS, then LDO generate IOVDD and AVDD , the LDO must be Isolated power supply?

Thanks a lot!

LTC2345-18 can't load module

Tingliwong — Sat, 12 Mar 2022 10:53:58 GMT

Hello,

I try to connect Quikeval to LTC2345-18(2326A-A) board by Linduino board.

That can't load module for this device. How i solve this problem?

Why dose my AD7124-8 read Id 0x16？

LLL1997 — Thu, 17 Feb 2022 07:17:54 GMT

Reliability Test Report of AD5242

Clt — Thu, 10 Feb 2022 01:33:04 GMT

Hi,

I would like to request the reliability test report of AD5242BRZ1M.

The reliability test report is not available on ADI's website.

Please assist. Much thanks.

AD9083: How the Trigger signal works with SYSREF

NanLi — Mon, 13 Dec 2021 03:16:39 GMT

Hi everyone,

I want to know how the "Trigger" signal works with SYSREF,

the logic relationship between them is "and"/"or" or some else?

I only find few description in AD9083 datasheet.

Regards,

Nan

Ad9253 abnormal sampling waveform

jys031006 — Mon, 06 Dec 2021 06:01:29 GMT

Hello, we encountered a problem when using ad9253bcpz-105. The problem is: after power on, when using 25m sampling, 50m sampling and 100m sampling, the waveform is abnormal. Occasionally, we power off and restart once or twice. During 50m sampling, we can get a normal waveform.

The hardware schematic diagram and PCB configuration are as follows:

(1) The working mode of ad9253 is: CSB pull up; SDIO / OLM pull up; SCLK / DTP pulled down;

(2) The data line and clock line use LVDS mode. The sampling clock of ad9253 is generated by ad9516-4. The data line is connected to Altera's FPGA and terminated with 100 ohm resistance.

(3) The data line and clock DCO and FCO are equal in length, and the length of a single line is between 36mm and 38mm;

(4) Ad9253 uses internal benchmark;; This set of clock and power supply for AD was previously used on ad9233; No abnormality;

Our FPGA engineers have adjusted the sampling timing for many days, which has no effect; Because the ad9253 also has problems in 25m and 50m sampling, it is reasonable that there should be no timing problem in low frequency. Please check it for me; Time is urgent, waiting for your reply!

thank you!

so many chips of AD1674's REF OUT is 2.5V, not 10V. why?

137143361 — Wed, 24 Nov 2021 07:01:51 GMT

pin 8 of AD1674 is REF OUT, and the voltage is 10V. But for the chips we purchased, there are two batches (model AD1674ARZ #1322 206836.1, and one batch of AD1674BRZ) whose REF OUT output is 2.5V. The ADC function seems normal. Are these IC products customized for some users, or these chips is damaged ?

fast Fourier transform (FFT) and extract signal power

chenyiren — Wed, 24 Nov 2021 02:08:33 GMT

Hello ! This is a process for extracting signal power and DC offset power after fft . The code is from Maxim Integrated Products, Inc.I want to know when we calculate the span of the input frequency, Why do we use max(round(numpt/200), 5), what do 200 and 5 mean?

And why spanh = 2 ?