Hello, we encountered a problem when using ad9253bcpz-105. The problem is: after power on, when using 25m sampling, 50m sampling and 100m sampling, the waveform is abnormal. Occasionally, we power off and restart once or twice. During 50m sampling, we can get a normal waveform.
The hardware schematic diagram and PCB configuration are as follows:
(1) The working mode of ad9253 is: CSB pull up; SDIO / OLM pull up; SCLK / DTP pulled down;
(2) The data line and clock line use LVDS mode. The sampling clock of ad9253 is generated by ad9516-4. The data line is connected to Altera's FPGA and terminated with 100 ohm resistance.
(3) The data line and clock DCO and FCO are equal in length, and the length of a single line is between 36mm and 38mm;
(4) Ad9253 uses internal benchmark;; This set of clock and power supply for AD was previously used on ad9233; No abnormality;
Our FPGA engineers have adjusted the sampling timing for many days, which has no effect; Because the ad9253 also has problems in 25m and 50m sampling, it is reasonable that there should be no timing problem in low frequency. Please check it for me; Time is urgent, waiting for your reply!
thank you!
