inputs are all floating?
This is expected and normal. The FIFO in the AD9122 serves as an interface
between the two clock domains inside of the DAC, the DCI domain and the DACCLK
domain. The read side of the FIFO (DACCLK domain) still runs when there is no
input signal and DCI, as long as a valid DAC clock is connected to the device.
The tones being observed are from looping of the initial data in
the FIFO. The level of these tones can be different from power on to power on
but their locations will be always at sub-multiples of the DACCLK freq.