Analog.com Analog Dialogue Wiki English
Analog.com Analog Dialogue Wiki 简体中文
EngineerZone
EngineerZone
  • Site
  • User
  • Site
  • Search
  • User
EngineerZone
EngineerZone
  • Log in
  • Site
  • Search
  • Log in
  • Home
  • Blogs ⌵
    • EngineerZone Spotlight
    • The Engineering Mind
  • Browse ⌵
    • All Groups
    • All Members
  • Support ⌵
    • 3D ToF Depth Sensing
    • Amplifiers
    • Analog Microcontrollers
    • Analysis Control Evaluation (ACE) Software
    • Audio
    • Clock and Timing
    • Condition-Based Monitoring
    • Data Converters
    • Design Tools and Calculators
    • Direct Digital Synthesis (DDS)
    • Embedded Vision Sensing
    • Energy Monitoring and Metering
    • FPGA Reference Designs
    • Industrial Ethernet
    • Interface and Isolation
    • Low Power RF Transceivers
    • MEMS Inertial Sensors
    • Motor Control Hardware Platforms
    • Optical Sensing
    • Power By Linear
    • Processors and DSP
    • Reference Circuits
    • RF and Microwave
    • Signal Chain Power (SCP)
    • Speech Processing Solutions
    • Switches/Multiplexers
    • Temperature Sensors
    • Video
    • Wide Band RF Transceivers
    • Wireless Sensor Networks Reference Library
  • My EZ
  • More
  • Cancel
  • 主页
  • 浏览 ⌵
    • 收件箱
    • 个人设置
    • 会员
    • 专区列表
  • 论坛专区 ⌵
    • 放大器专区
    • 精密转换器专区
    • 音频专区
    • ADE电能计量专区
    • MEMS和传感器专区
    • 接口和隔离专区
    • Power 中文专区
    • ADUC微处理器专区
    • 锁相环专区
    • 开关和多路复用器专区
    • 温度传感器
    • 基准电压源专区
    • 资源库
    • 论坛使用指南
    • 技术支持参考库
    • 在线研讨会
    • 论坛社群活动
    • 论坛激励活动
  • More
  • Cancel
High-Speed DACs
  • Data Converters
  • More
High-Speed DACs
Documents AD9734: multichip SYNCHRONIZATION
  • Q&A
  • Discussions
  • Documents
  • File Uploads
  • Video/Images
  • Tags
  • Managers
  • More
  • Cancel
  • New
High-Speed DACs requires membership for participation - click to join
  • +Documents
  • AD9115: Limit for the current the part can deliver
  • AD9116_power supply 
  • AD9117: How do I estimate the overall DAC pipeline delay?
  • AD9122-M5375-EBZ Harmonics at 90MHz
  • AD9129 - Compatible data generator ad9129
  • AD9129 - Highest RF output frequency spectrum supported
  • AD9129 - Mix-Mode function
  • AD9129 -  Clock source and buffer recommendation
  • AD9129 datasheet clarifications
  • AD9135/AD9136 - Are there evaluation boards available?
  • AD9135/AD9136 - Does the AD9135/AD9136 support deterministic latency/multi-chip synchronization?
  • AD9135/AD9136 - How do I select between the two parts?
  • AD9135/AD9136 - What are the key specifications for my application?
  • AD9135/AD9136 - What is the max data rate the AD9135/AD9136 supports?
  • AD9142A Byte Interface Mode
  • AD9142A: error message when setting up offsets ( IDAC/QDAC, IQ phase& Gain ADJ )
  • AD9144 - Does the AD9144 support deterministic latency/multi-chip synchronization?
  • AD9144 - Is this a JESD204B SERDES high-speed DAC product?
  • AD9144 - What evaluation boards are available?
  • AD9144 - What is the difference between the DPG3 compatible boards and the FMC evaluation board?
  • AD9144 - What JESD204B SERDES modes are available on the AD9144?
  • AD9148: Unused channel / Unused pins
  • AD9712 general recommendations
  • AD9716 - Logic Levels at AVDD=3.3V, DVDD=1.8V, DVDDIO=1.8V, CVDD=1.8V
  • AD9717: Pin connection
  • AD9726: Interface with the AD600
  • AD9726_Iout equation error
  • AD9734: multichip SYNCHRONIZATION
  • AD9734: Synchronize two DACs
  • AD9736 - Theta JC
  • AD9739: FPGA selection
  • AD9739: IRQ clearance
  • AD9739: May I leave SYNC_OUT and SYNC_IN pins unconnected?
  • AD9739: multichip synchronization
  • AD9739: Output amplitude DC-offset
  • AD9739A-FMC-EBZ with Zedboard
  • AD9739_AC coupling LVDS
  • AD9739_balun two sides
  • AD9739_CLK input model and little output power
  • AD9739_R2-EBZ  DAC Output stage termination
  • AD9742/AD9744 Exposed Pad
  • AD9742_several questions_DCOM and ACOM
  • AD9742_several questions_differential resistor
  • AD9744: Maximum sample rate
  • AD9747: Thermal Information
  • AD9748_REFLO pin
  • AD974: Antialiasing filter
  • AD9765 influence of the clocks
  • AD9767: Input timing for interleaved mode
  • AD9767: Load range
  • AD976A's Transfer function
  • AD977 ?jb
  • AD9774: CLK input voltage
  • AD9774: DAC output range and external buffer
  • AD9776: Maximum sample rate
  • AD9777 / AD9779: The two channel DACs, can they be used separately?
  • AD9777 max speed and timing query (SR#: 1200982)
  • AD9777: DATACLK can only be output pin
  • AD9777: Modulating the bandwidth
  • AD9779: Grounding and layout recommendation
  • AD977A: Driving the inputs
  • AD977A: is it possible to use one AD780 to be the ref voltage of 16 AD977A for +-10V range?
  • AD9780 driven by FMC Board Clock
  • AD9783: LVDS interface termination resistor
  • AD9783: read back value of the Hardware Version of the AD9783
  • AD9786: Current output voltage calculation
  • AD9786: Propagation delay
  • AD9786: Reset timing
  • AD9786: Thermal pad connection
  • AD9788: Can I bypass the NCO (numerically controlled oscillators)?
  • AD9789: AD9789EBZ and AD9789-Mix-EBZ difference
  • Alias Frequencies
  • Can AD9763's NC pins (i.e. pin 33 & 34) be driven or must they be definitely left floating?
  • Can fs/4 spurs be reduced or eliminated by factory calibration, or any other method, on the AD9739/AD9739A?
  • DAC AD9122 and AD-FMCJESDADC1-EBZ wrt external trigger
  • DAC REFOUT Current
  • Datasheet errors in the AD9736/5/4
  • Digital Pattern Generator?
  • Driving the clock of AD9739 DAC
  • Evalboards use DAC "N" output and the datasheet uses the DAC "P" output. Which is correct?
  • FAQ: What is the latency of the AD9739?
  • FAQ: What is the latency of the AD9789?
  • High-speed ADC for non-uniform sampling
  • HIGH-SPEED DAC SUPPORT COMMUNITY
  • How accurate is the AD9739's output impedance of 70ohms?
  • Impedance matching when AD9717 or AD9779A interfaced with ADL5375
  • improve your AD9739's SNR
  • Output pins
  • Should I connect to ground the CMLI, CMLQ, FSADJI and FSADJQ pins?
  • Some soldered jumpers on the AD9122 Evalboard are not as per default settings mentioned in User Guide
  • SPI communication issue between AD9106 EBZ and TI ezdsp f28335
  • The AD9146 Filters, Premodulator and modes?
  • What is the difference between the DPG3 compatible boards and the FMC evaluation board?
  • What is the highest RF output frequency supported by the AD9144?
  • What is the latency of the AD9777,5,3 DAC family?
  • What is the max data rate the AD9144 supports?
  • What is the Psi-jt for the AD9142A package (72-pin LFCSP)?
  • What is the tuning resolution of the output frequency of these devices?
  • What JESD204B SERDES modes are available on the AD9135/AD9136?
  • Where can I find the BOM, schematics and gerbers for AD9119-MIX-EBZ?
  • Why do I see a very large signal at 2*fdac for the AD9739 DAC?

AD9734: multichip SYNCHRONIZATION

Q 

1, I am using  four AD9734s. Because DACCLK is divided by 2 to create
DATACLK_OUT, the phase of DATACLK_OUT can be 0° or 180°, it's uncertain. As the
red line shown (attache figure 1), the DATACLK_OUT is also used to transit the
incoming data to the DACCLK domain. So for multiple AD9734s, even though their
DATACLK_INs and DACCLKs have the same phase, because of the Dac Sampling
Signal's(Red line) uncertainty of different AD9734s, the sequence of feeding
D1A and D2A into DAC CORE is different. So multiple AD9734s' DAC output can't
be synchronized, that is, compared to other DAC's output, some DAC' output may
lag one DACCLK.
2, Also,I found another problem: after I configured the MODE REGISTER (0x00)and
FSC(0x02,0x03), the timings of multiple DAC output may be variable. For
example, before writing register, the first three DAC output is good and the
fourth DAC output lags one DACLK, but after writing registers, the first two
DAC output is OK and the third and fourth DAC output lags one DACCLK. Whether
the operation to register can make influence to the DACCLK?
Would you please give me some advices about the two problems?

 

A 

The AD9734 has two internal timing domains. The first domain is the digital
inputs which are clocked by the DATA_CLK_IN. The second domain is where the DAC
actually gets a clock from the DAC_CLK_IN. These domains run independently and
there is no required timing relationship (no set up and hold requirement)
between the DATACLK_IN and DAC_CLK_IN. The key to the input domain handing off
the digital data to the DAC domain is that there is an internal FIFO that
automatically makes up for any phase difference between DATACLK_IN and
DAC_CLK_IN. The big issue with this is that anytime the DAC powers up, the FIFO
can come up in one of several valid different states, all of which cause a
different delay from the digital inputs to the DAC output. I'm sure this is why
you are seeing the problem.

The FIFO can be turned off, but when it is turned off, then there are timing
requirements that must be met between DATACLK_IN and DAC_CLK_IN. These timing
requirements are given in table 28 on page 55 of the AD9734 rev A datasheet.

The solution that we have recommended in the past for synchronizing multiple
AD9734s is that a special circuit must be built in the FPGA/digital driver.
This circuit takes the DATACLK_OUT from the first AD9734 and uses it to sample
the DATACLK_OUT signals from all of the other AD9734s. If it detects that any
of the DATACLK_OUT signals are inverted from the first one, then it
automatically inverts the DATACLK_IN for that AD9734. In this way, strict
timing relationships can be achieved between the DATACLK_OUT, DATACLK_IN and
DACCLK on all AD9734s.
Attachments:
AD9734_multichipSYNCHRONIZATION.docx
  • ad9734
  • Share
  • History
  • More
  • Cancel
Comments
Anonymous
Related
 
社交网络
快速链接
  • 关于ADI
  • Partners
  • 模拟对话
  • 职业
  • 联系我们
  • 投资信息
  • 新闻中心
  • 质量和可靠性
  • 办事处与代理商
  • Analog Garage
语言
  • English
  • 简体中文
  • 日本語
  • Руccкий
电子快讯

欲获得最新ADI产品、设计工具、培训与活动的相关新闻与文章,请从我们的在线快讯中选出您感兴趣的产品类别,每月或每季度都会发送至您的收件箱。

订阅
Switch to mobile view
Analog Logo
© 1995 - 2021 Analog Devices, Inc. All Rights Reserved 沪ICP备09046653号-1
  • ©
  • 1995 - 2021 Analog Devices, Inc. All Rights Reserved
  • 沪ICP备09046653号-1
  • 网站地图
  • 隐私和保密政策
  • 隐私设置
  • 使用条款
 
Social
Quick Links
  • About ADI
  • Partners
  • Analog Dialogue
  • Careers
  • Contact us
  • Investor Relations
  • News Room
  • Quality & Reliability
  • Sales & Distribution
  • Analog Garage
Languages
  • English
  • 简体中文
  • 日本語
  • Руccкий
Newsletters

Interested in the latest news and articles about ADI products, design tools, training and events? Choose from one of our 12 newsletters that match your product area of interest, delivered monthly or quarterly to your inbox.

Sign Up
Switch to mobile view
Analog Logo
© 1995 - 2021 Analog Devices, Inc. All Rights Reserved 沪ICP备09046653号-1
  • ©
  • 1995 - 2021 Analog Devices, Inc. All Rights Reserved
  • 沪ICP备09046653号-1
  • Sitemap
  • Privacy & Security
  • Privacy Settings
  • Terms of use
EngineerZone Uses cookies to ensure you get the best experience in our community. For more information on cookies, please read our Privacy & Security Statement.