The Engineering Mind
3D ToF Depth Sensing
Clock and Timing
Design Tools and Calculators
Direct Digital Synthesis (DDS)
Embedded Vision Sensing
Energy Monitoring and Metering
FPGA Reference Designs
Interface and Isolation
Low Power RF Transceivers
MEMS Inertial Sensors
Motor Control Hardware Platforms
Power By Linear
Processors and DSP
RF and Microwave
Wireless Sensor Networks Reference Library
Datasheet errors in the AD9736/5/4
High-Speed DACs requires membership for participation - click to join
AD9115: Limit for the current the part can deliver
AD9117: How do I estimate the overall DAC pipeline delay?
AD9122-M5375-EBZ Harmonics at 90MHz
AD9129 - Compatible data generator ad9129
AD9129 - Highest RF output frequency spectrum supported
AD9129 - Mix-Mode function
AD9129 - Clock source and buffer recommendation
AD9129 datasheet clarifications
AD9135/AD9136 - Are there evaluation boards available?
AD9135/AD9136 - Does the AD9135/AD9136 support deterministic latency/multi-chip synchronization?
AD9135/AD9136 - How do I select between the two parts?
AD9135/AD9136 - What are the key specifications for my application?
AD9135/AD9136 - What is the max data rate the AD9135/AD9136 supports?
AD9142A Byte Interface Mode
AD9142A: error message when setting up offsets ( IDAC/QDAC, IQ phase& Gain ADJ )
AD9144 - Does the AD9144 support deterministic latency/multi-chip synchronization?
AD9144 - Is this a JESD204B SERDES high-speed DAC product?
AD9144 - What evaluation boards are available?
AD9144 - What is the difference between the DPG3 compatible boards and the FMC evaluation board?
AD9144 - What JESD204B SERDES modes are available on the AD9144?
AD9148: Unused channel / Unused pins
AD9712 general recommendations
AD9716 - Logic Levels at AVDD=3.3V, DVDD=1.8V, DVDDIO=1.8V, CVDD=1.8V
AD9717: Pin connection
AD9726: Interface with the AD600
AD9726_Iout equation error
AD9734: multichip SYNCHRONIZATION
AD9734: Synchronize two DACs
AD9736 - Theta JC
AD9739: FPGA selection
AD9739: IRQ clearance
AD9739: May I leave SYNC_OUT and SYNC_IN pins unconnected?
AD9739: multichip synchronization
AD9739: Output amplitude DC-offset
AD9739A-FMC-EBZ with Zedboard
AD9739_AC coupling LVDS
AD9739_balun two sides
AD9739_CLK input model and little output power
AD9739_R2-EBZ DAC Output stage termination
AD9742/AD9744 Exposed Pad
AD9742_several questions_DCOM and ACOM
AD9742_several questions_differential resistor
AD9744: Maximum sample rate
AD9747: Thermal Information
AD974: Antialiasing filter
AD9765 influence of the clocks
AD9767: Input timing for interleaved mode
AD9767: Load range
AD976A's Transfer function
AD9774: CLK input voltage
AD9774: DAC output range and external buffer
AD9776: Maximum sample rate
AD9777 / AD9779: The two channel DACs, can they be used separately?
AD9777 max speed and timing query (SR#: 1200982)
AD9777: DATACLK can only be output pin
AD9777: Modulating the bandwidth
AD9779: Grounding and layout recommendation
AD977A: Driving the inputs
AD977A: is it possible to use one AD780 to be the ref voltage of 16 AD977A for +-10V range?
AD9780 driven by FMC Board Clock
AD9783: LVDS interface termination resistor
AD9783: read back value of the Hardware Version of the AD9783
AD9786: Current output voltage calculation
AD9786: Propagation delay
AD9786: Reset timing
AD9786: Thermal pad connection
AD9788: Can I bypass the NCO (numerically controlled oscillators)?
AD9789: AD9789EBZ and AD9789-Mix-EBZ difference
Can AD9763's NC pins (i.e. pin 33 & 34) be driven or must they be definitely left floating?
Can fs/4 spurs be reduced or eliminated by factory calibration, or any other method, on the AD9739/AD9739A?
DAC AD9122 and AD-FMCJESDADC1-EBZ wrt external trigger
DAC REFOUT Current
Datasheet errors in the AD9736/5/4
Digital Pattern Generator?
Driving the clock of AD9739 DAC
Evalboards use DAC "N" output and the datasheet uses the DAC "P" output. Which is correct?
FAQ: What is the latency of the AD9739?
FAQ: What is the latency of the AD9789?
High-speed ADC for non-uniform sampling
HIGH-SPEED DAC SUPPORT COMMUNITY
How accurate is the AD9739's output impedance of 70ohms?
Impedance matching when AD9717 or AD9779A interfaced with ADL5375
improve your AD9739's SNR
Should I connect to ground the CMLI, CMLQ, FSADJI and FSADJQ pins?
Some soldered jumpers on the AD9122 Evalboard are not as per default settings mentioned in User Guide
SPI communication issue between AD9106 EBZ and TI ezdsp f28335
The AD9146 Filters, Premodulator and modes?
What is the difference between the DPG3 compatible boards and the FMC evaluation board?
What is the highest RF output frequency supported by the AD9144?
What is the latency of the AD9777,5,3 DAC family?
What is the max data rate the AD9144 supports?
What is the Psi-jt for the AD9142A package (72-pin LFCSP)?
What is the tuning resolution of the output frequency of these devices?
What JESD204B SERDES modes are available on the AD9135/AD9136?
Where can I find the BOM, schematics and gerbers for AD9119-MIX-EBZ?
Why do I see a very large signal at 2*fdac for the AD9739 DAC?
Datasheet errors in the AD9736/5/4
Is the datasheet 288522419AD9734_5_6_0.pdf the latest version? There seem to be
pinout errors on page 54 og 68.
What connections are reccommended for the 2 unused bits in this 12-bit device?
I assume I want to drive DB2 through DB13 with my 12-bit data.
Must the RESET signal be synchronous with DATACLK_IN, or CLK? What is the
required duration of RESET?
First off, the schematic of the rev F eval board in the AD9736/5/4 rev 0
datasheet has errors. Several of the pin numbers for the AD9736 are incorrect.
I've attached a correct rev F schematic for your reference. The errors in pin
numbers are located around the data inputs.
I just noticed one other mistake on the AD9736 datasheet. In the correct
schematic I have attached, the pins on the AD9736 are called out as
LVDS13......to LVDS0. The netlisted pins on the schematic are listed as DB0 to
DB13 for these same pins. However, if you look at the pin function description
on page 12 of the datasheet, the pins on the AD9736 are referred to as DB13 to
DB0, but this bus is reversed with respect to the DB13 to DB0 on the schematic.
Maybe you've already noticed this. At the end of the day, the MSB and LSB are
in the right order on page 12, pin numbers are also correct on page 12, and the
pin numbers are correct on the rev F schematic I've attached to this email. I
apologize for the confusion, we've got to fix this.
The AD9735 is the 12 bit member of the AD9736 family which includes the 14 bit
AD9736, the 12 bit AD9735 and the 10 bit AD9734. However, we only make one eval
board and depending on the customer request, we stuff the board with either the
14,12, or 10 bit part. Between the three eval boards, the data bus is always
MSB (most significant bit) justified. That is, if you look at the eval board
schematic, the pins that are labelled LVDS13N and LVDS13P are the MSB pins
(pins K13,K14). These same pins will be the MSB on the AD9735 and on the
AD9734. On the AD9735, pins M2,M1,N1,P1 will be no connects, as they would
represent the 13th and 14th bits in this TxDAC family. On the AD9734, pins
M2,M1,N1,P1,N2,P2,N3,P3 will be no connects, as they would represent the 11th
and 12th bits in this TxDAC family.
The RESET pin is indeed asynchronous, does not have be coincident with clock.
The required duration is no longer than ten DAC clock cylces.
Privacy & Security Statement
Accept & Continue