Q
Question 1)
Is the datasheet 288522419AD9734_5_6_0.pdf the latest version? There seem to be
pinout errors on page 54 og 68.
Question 2)
What connections are reccommended for the 2 unused bits in this 12-bit device?
I assume I want to drive DB2 through DB13 with my 12-bit data.
Question 3)
Must the RESET signal be synchronous with DATACLK_IN, or CLK? What is the
required duration of RESET?
A
First off, the schematic of the rev F eval board in the AD9736/5/4 rev 0
datasheet has errors. Several of the pin numbers for the AD9736 are incorrect.
I've attached a correct rev F schematic for your reference. The errors in pin
numbers are located around the data inputs.
I just noticed one other mistake on the AD9736 datasheet. In the correct
schematic I have attached, the pins on the AD9736 are called out as
LVDS13......to LVDS0. The netlisted pins on the schematic are listed as DB0 to
DB13 for these same pins. However, if you look at the pin function description
on page 12 of the datasheet, the pins on the AD9736 are referred to as DB13 to
DB0, but this bus is reversed with respect to the DB13 to DB0 on the schematic.
Maybe you've already noticed this. At the end of the day, the MSB and LSB are
in the right order on page 12, pin numbers are also correct on page 12, and the
pin numbers are correct on the rev F schematic I've attached to this email. I
apologize for the confusion, we've got to fix this.
The AD9735 is the 12 bit member of the AD9736 family which includes the 14 bit
AD9736, the 12 bit AD9735 and the 10 bit AD9734. However, we only make one eval
board and depending on the customer request, we stuff the board with either the
14,12, or 10 bit part. Between the three eval boards, the data bus is always
MSB (most significant bit) justified. That is, if you look at the eval board
schematic, the pins that are labelled LVDS13N and LVDS13P are the MSB pins
(pins K13,K14). These same pins will be the MSB on the AD9735 and on the
AD9734. On the AD9735, pins M2,M1,N1,P1 will be no connects, as they would
represent the 13th and 14th bits in this TxDAC family. On the AD9734, pins
M2,M1,N1,P1,N2,P2,N3,P3 will be no connects, as they would represent the 11th
and 12th bits in this TxDAC family.
The RESET pin is indeed asynchronous, does not have be coincident with clock.
The required duration is no longer than ten DAC clock cylces.