analog frontend. Two DAC's used for synchronous transmission of two baseband
channels. To sync the DAC's we enable FIFO controllers on both chips to monitor
FIFOSTAT registers (reg.7 7:6) and change value of PHOF register (reg.7 1:0) to
align the DAC's output signal. Our system software performs initial ailgnment
of the DAC's output signals during the startup and monitoring of the sync after
the startup. During the monitoring of the FIFOSTAT value on the DAC's we
observe random variations of the FIFOSTAT value during normal work of the
system. This leads our software to show incorrect sync status (we see that
DAC's are out of sync but the system works okay) and also not able to recover
the system when we really lost the DAC sync.
Seems we have resolved our problem with the AD9734 DAC's synchronization. The
problem with the change of FIFOSTAT was due to the phase relationship between
the DACCLK_IN and DACCLK clock signals. The initial parameters of our design
give us the situation that we have phase of the these clock close to each
other. This situation leads to incorrect sampling of read FIFO pointer value by
the DACCLK clock. We conclude this looking on Figure 82 of AD9734 datasheet the
read pointer (signal from DATACLK_IN domain) value is directly sampled by the
signal from DACCLK domain. We suppose that due to this things we see changes
of the FIFOSTAT values but have the correct synchronization between the DAC's.
The issue has been resolved by changing the phase of the DACCLK_IN clock by
changing phase of the FPGA PLL clock that is produced from the DACCLK_OUT
clock. After changing the clock phase we have stable values from FIFOSTAT on
both DAC's and correct synchronization between the DAC's.