should be smaller than 3 degree, If I use design synchronization circuit shown
in Figure 1, and DACLCK is 1GHz, AD9739's output may be several MHz ~ 400MHz,
can the phase difference between the two DAC's output can be smaller than 3
If we assume worse case output..........the period of a sinewave at 400 MHz is
2.5 nsec. If both DAC's are producing a sinewave at 400 MHz and outputs need
to be matched within 3 degrees (i.e. +/-3 degrees relative to 360 degree period
corresponds to one wave leading or lagging other
waveform)..................than the delay mismatch between both DAC outputs can
be no greater than 42 psec (2.5 nsec x 3/180).
This sort of delay matching will be difficult to achieve for following reasons:
1) Internal clock path delay variations: The actual propagation delay (due to
clock tree) between the DACCLK input and actual DAC update is sensitive to
process, voltage and temperature variations. The mismatch could be up to 100
psec for devices from at the extreme process corners.
2) Some sort of low pass filter will precede each DAC. Depending on component
tolerances, you may see a "mismatch" in group delay variation between both
filters which causes mismatch in phase.
3) Delay propogation skew between ADCLK925 outputs could be up to 10 psec.
4) Board layout needs to be very tight.
The good news is that the lower frequency (i.e. 200 MHz), the wider the
tolerable delay mismatch becomes since period of sinewave becomes greater.
Hence, for baseband I/Q applications where signal power extends from DC to 400
Mhz and low order QAM (i.e. QPSK, 16QAM), this sort of mismatch from 1 and 3
may be still reasonable...........depends on system designer.
Note, if this is a "Baseband IQ application (i.e. high symbol rate QAM for
pt-to-pt), one may also want to consider the AD9122 Dual DAC operating with 2X
interpolation. Having DAC's on same IC significantly reduces problem 1 and 3