I'm having problems with locking of the data receiver and I'm thinking that
this may be because of the way I connect the FPGA to the DAC. I connect the
data and DCI clock via capacitors.
Does the AD9739 have auto biasing for the LVDS inputs and can I use capacitive
coupling or do I have to use DC coupling. The datasheet doesn't really say.
What would be the best way to connect a Virtex-5 using LVDS-25 output buffers
to a AD9739?
The reason I prefer capacitive coupling is that the two devices are powered
from different power supplies that have different ramp up times.
DC coupling is possible if I replace the capacitors on the board with 0 ohm
I am not aware of that has ac coupled the digital interface between FPGA and
the AD9739. Our test platform is based on the DPG2 (digital pattern generator)
which has an FPGA directly connected to a digital interface connector which is
used to interface to the AD9739 EVB (i.e. different supply domains and no ac
coupling caps) and we have never had any issues. Bottom line..........why
theory suggests ac coupling is possible if signal content on signal lines is
well above the high pass cut-off freq formed by the ac coupling capacitor, I
would suggest you used 0 ohm resistors instead.
Note, the inclusion of "pads" to accommodate these capacitors could result in a
sub-optimum PCB layout where the desired 100 ohm differential impedance of the
transmission line may be disturbed by impedance mismatch of the pads. This
could lead to a poorer "eye diagram" of the digital signals appearing at the
AD9739 input. Regards.