datasheet. However, I found when AD9739's clock pins are connected to CLKP and
CLKN, there seemed to be a voltage degradation at the DACCLK input. Therefore,
I would like to know what the input impedance and structure of the clock input.
Or, is there an equivalent DACCLK input circuit for this part. One more
question,If using one ADCLK914 to drive two AD9739 simultaneously. Ifound that
the DCO outputs of these two parts have a random phase error when powering up.
Do you think one ADCLK914 can be used to drive two parts? And what could be the
reason for this phase error. How can we deal with it or synchronize two DCO
Also note that the AC coupling capacitor of 2.4 nF (on our eval board) could
present a problem since they are not ideal at 2.5GHz. The series impedance
presented by this cap can reduce the signal levels. When coupled with board
parasitics, it becomes difficult to predict the behavior unless accurately
modeled. We have not had any problems with our EVB and this issue has not been
raised by other customers, but this may simply mean that the 9739 is working
properly in spite of the clock swing being less than 1.2V p-p. We would
recommend wideband capacitors that have good RF behavior at 2.5 GHz (see link
below), if this were to be the case.What is their purpose in driving the two
DACs simultaneously? Do you need to synchronize the DAC outputs? In which case
simply driving the DACs with the same driver will not work. You would have to
use the internal multi-chip synchronization feature for that. Unfortunately, we
have run into some issues using this feature. We are currently investigating
the “robustness” of the AD9739 synchronization controllers which results in the
“master device” unable to establish lock consistently under all conditions.
It may be good to wait until we resolve the limitations that are causing this