Can I MUX the data over the AD9162 JESD204B interface to share JESD pins between two digital chips?

Question:

Can I mux the data over the JESD204B interface like the following: ASIC to use lanes 4-7, and FPGA to use lane 0-3 or vice versa?

Resolution:

No, Lane 0 must used whenever SERDES data is needed.

Tags: high-speed dacs AD9162 SERDES JESD204B KA-01009 ad9164
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