Can I mux the data over the JESD204B interface like the following: ASIC to use lanes 4-7, and FPGA to use lane 0-3 or vice versa?
Resolution:No, Lane 0 must used whenever SERDES data is needed.
AD9164
Recommended for New Designs
The AD91641 is a high performance, 16-bit digital-to-analog converter (DAC) and direct digital synthesizer (DDS) that supports update rates to 6 GSPS....
Datasheet
AD9164 on Analog.com
AD9162
Recommended for New Designs
The AD9162 is a high performance, 16-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture...
Datasheet
AD9162 on Analog.com
Can I mux the data over the JESD204B interface like the following: ASIC to use lanes 4-7, and FPGA to use lane 0-3 or vice versa?
Resolution:No, Lane 0 must used whenever SERDES data is needed.