External clock on the AD9164 FMC eval board

Question: The external clock input on the AD9164-FMC-EBZ isn't working. ACE software selects to change it, but nothing happens on the eval board. Resolution: This is a known issue with boards that were produced near release time. The firmware programmed on the eval board does not toggle the control signal for the RF switch, making it such that the eval board will always use the on-board clock and won't use the external clock. This applies to AD9162-FMC-EBZ, AD9164-FMC-EBZ, and may apply to the AD9162-FMCB-EBZ and AD9164-FMCB-EBZ that have B-grade released parts loaded on them with date codes #1615. The issue applies to a small number of boards. The boards must be re-programmed at the factory with correct firmware. The customer should arrange return of the board with the local ADI support person (FAE or TSM), who should contact the ADI factory and arrange the return, re-program, and re-ship back to the customer.

AD9162 Temp Sensor Cal - Partial Start-Up Seq

Question: Is there a partial/minimal start-up sequence that would allow SW to read the CODE_REF register but keep the rest of the DAC in a low power mode so the DAC’s self-heating is minimized? Resolution: Yes, you should be able to read the CODE_REF after you enable the bandgap reference: W | 0x058 | 0x03 | Enable the band gap reference (private). Then you should be able to continue the start-up sequence as normal.

AD9162 eval board grounding/decoupling

Question: Why is there power supply decoupling between VDDA25 and VNEG12 on the AD9162 eval board? And what is the purpose of the SA_GND? Answer: The DAC core swings between VDDA25 and VNEG12, so decoupling on both rails is a good idea. The rest of the DAC is referenced to ground, so decoupling from them to ground (VSS) is also a good idea. The SA_GND is a holdover from an earlier board. It is not needed, so on future designs, that domain will be eliminated and shorted to GND.

Time to change the AD9164 DAC clock frequency in NCO mode (DDS)

Question: If I change the DACCLK on the AD9164 when using it as a DDS , what is the recovery time? How fast can I change sample clock and tuning word? Answer: The part would need to re-lock the DAC clock DLL and clear out the NCO phase accumulator, which happens in a few hundreds of clock cycles. The safest method to do this would be to re-run the DAC start up sequence, which would add to the time to switch DAC clock frequency due to the series of SPI writes, but there is probably a subset of things that could be done, like perhaps disabling the DAC clock DLL, then re-enabling it, checking that the DLL re-locked, and then it should be good to go. This hasn't been characterized, but is a method the customer could try. The speed to change NCO frequency is dependent on the number of SPI register writes and the SPI programming speed. At 100 MHz SPI writes, a single register write can be made in 240 ns, with an approximate 20 ns for the NCO to hop to the new frequency using phase discontinuous switch mode.

How do I create signals for the AD9161, AD9162, AD9163, AD9164 and ADS7-V2?

Question: I am using the AD9163-FMCC-EBZ and ADS7-V2. How do I generate signals as I want (sines with different freqs. combinations) using the ADS7-V2 software? Can I use my own application (labview, matlab, etc) for this purpose? In other words, how can I load my digital words in the ADS7-V2 to obtain an analog signal in the AD9163 output? Resolution: You can use DAC Software Suite, which includes the DPG Downloader, to create many standard communication signal waveforms. You can also create your own waveforms in Matlab or any other software, save them, and import them into DPG Downloader and play them. This method is described in the User Guide on the Analog Devices Wiki site here: https://wiki.analog.com/resources/eval/dpg/ad916x-fmcx-ebz#using_external_files

Can I MUX the data over the AD9162 JESD204B interface to share JESD pins between two digital chips?

Question: Can I mux the data over the JESD204B interface like the following: ASIC to use lanes 4-7, and FPGA to use lane 0-3 or vice versa? Resolution: No, Lane 0 must used whenever SERDES data is needed.

Are there IBIS-AMI models for the AD9162 and AD9164?

Question: Is there an IBIS-AMI model for AD9162? If not, is there an existing IBIS-AMI model for a similar package / device that can be used to simulate the JESD204B interface? Resolution: No, there is no IBIS-AMI model for the AD9162. We suggest that the customer use the IBIS-AMI models for the AD9144 since the JESD core and PHY are the same design, and then recognize that the package model for the AD9144’s LFCSP will be “pessimistic” as compared to the BGA package for the AD9162. The belief is that if the customers design their boards to work with the AD9144, they can be confident that they’ll work with the AD9162 since it doesn’t have as much degradation as the AD9144’s package.

AD9164 Chirp Waveforms

Question: Do you have a user’s guide for creating chirp waveforms using the AD9164 with the pattern generator board? Resolution: There is no documentation on the chirp generator in DPG Downloader. The usage of the generator is straightforward: set a start frequency, a stop frequency, and a data rate, and the vector spreads that frequency change over the record length.