ADV7125: Run off 3.3V supply

Question I am confused by the data sheet. Can the ADV7125 run with a 3V3 power rail? If so, what parameters are effected? From the application schematic, the ground pins on the video output connector appear to be connected to the main board ground plane, i.e. DGRND. Is this correct, or should the analogue grnd pins on the video connector be connected to AGRND? Answer Yes it can run off 3.3 volts - hence the specifications on page 3 of the datasheet representing our own results with a 3V3 supply. I assume you ask because the pinlist on page 7 designates Vaa as "5V +/- 5%". There is no VDD pin on this part only 3 VAA pins. There is not a lot of digital circuitry on this part and hence no requirement for a separate digital supply pin. All three VAA pins should be fed from a clean, decoupled analog supply line via wide low inductance tracks. The recommended filtering for the supply is a PI filter consisting of a C to ground, series inductor in the supply line followed by a C to ground. This will provide isolation between the converter power supply and the rest of the power line.

Question We are designing a board where the digital inputs to an ADV7125 (data, clock and control) are coming from a Xilinx FPGA. There will be a short time, while the FPGA is configuring, where the inputs to the ADV7125 will be floating. Do you have any recommendations for the ADV7125 in this regard? Answer The digital inputs to the ADV7125 should not be left floating - if they are left floating they will be opened to surrounding noise which can make the pins high or low. The digital inputs should be connected via resistors from the FPGA to the ADV7125. The control pin SYNC should be connected to ground via a zero ohm resistor. The control pin BLANK should be connected high via a zero ohm resistor. Since the output of the FPGA is either going to be at logic 0 or logic 1, then the digital inputs to the ADV7125 should be connected via resistors and not tied to ground. The o/p clock should be connected to the ADV7125 clock input.

Floating Inputs to ADV7125

Question I’m designing a board where the digital inputs to an ADV7125 (data, clock and control) are coming from a Xilinx FPGA. There will be a short time, while the FPGA is configuring, where the inputs to the ADV7125 will be floating. Do you have any recommendations for the ADV7125 in this regard? Answer The digital inputs to the ADV7125 should not be left floating - if they are left floating they will be opened to surrounding noise which can make the pins high or low. The digital inputs should be connected via resistors from the FPGA to the ADV7125. The control pin SYNC should be connected to ground via a zero ohm resistor. The control pin BLANK should be connected high via a zero ohm resistor. Since the output of the FPGA is either going to be at logic 0 or logic 1, then the digital inputs to the ADV7125 should be connected via resistors and not tied to ground. The o/p clock should be connected to the ADV7125 clock input.