AD9789 start-up sequence--Is it okay to enable the mu controller first, then supply DAC clock?

Question: For AD9789, is it OK or not turning on the DAC_CLK (0x32 CLK_DIS = 1) after enabling the Mu delay controller (0x33 MU_EN = 1)? Resolution: The order of register programming might be okay. There is a concern that by enabling the Mu controller first, then providing a DAC clock input, the mu controller may not end (or lock) at the desired phase. The recommended sequence ensures that there is a stable clock running first, so all logic is in a known state before the Mu controller is enabled. Customer would need to check that the mu controller consistently locks at the target phase value in a variety of environmental conditions before committing this sequence to production.

AD9789: AD9789EBZ and AD9789-Mix-EBZ difference

Question There are two kinds of evaluation boards for AD9789, normal and mix mode. What is the difference between them since only one schematic is listed on the page: http://wiki.analog.com/resources/eval/dpg/eval-ad9789 Especially, is the output RF transformer used on both boards same? Answer We now only ship the Normal mode board because we changed the transformer to one that can support both Normal and Mix-mode . That is why there is only one schematic now. It shows the JTX-2-10T transformer.

Question We are seeing folded harmonics in our tests, can you help. Answer Folded 2nd harmonics are common and should be expected. The level varies basedon several things like DAC clock balance and DAC output balance. It is affectedby output balun balance, and it varies from board to board. If the PCBt has poorer balance than the board used in our quick start guide you will seeworse performance.

What is the latency of the AD9789?

Q. What is the latency of the AD9789? ----------------------------------------------------------------------- A. Define latency as the elapsed time from a sample clocked at the input to the AD9789 until the analog output begins changing. The latency of the AD9789 depends on which digital blocks are enabled in the datapath. The time can be approximated by using the calculation method provided below. For each block in the table below that is enabled, take the latency number, and multiply it by the period of the clock listed in the units column to determine the latency through that block. Sum all of the calculated latencies together to determine the latency through the device. This method is not exact, but the approximation is sufficient for most applications. block latency units input 1 BR QAM 1 BR SRRC 44 BR/2 2x0 28 BR/4 2x1 13 BR/8 2x2 10 BR/16 2x3 5 BR/32 2x4 5 BR/64 RC 6 FS*16 DDS 5 FS*16 sum 3 FS*16 16x 144 FS BR = period of baud rate clock FS = period of DAC clock Note that the highest latency values are calculated for those blocks that run at or close to the baud rate.

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AD9789 Production
The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC)...
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