AD9786: Current output voltage calculation

Question I found a problem with one of my customers where AD9786 full scale output power under single tone test condition is only 3 dBm, much lower than the specified value 10dBm, so they would like to confirm if max. output power of AD9786 is able to achieve 10 dBm? Answer We don't actually say you can get 10dBm out of the DAC. We specify that the full scale current is 20mA, and if you drive that into 50 ohms on each DAC output, you will get 1V p-p on each DAC output. A 1V peak signal corresponds to 700mV RMS, which in turn equals 10dBm. That's probably where they are calculating the 10dBm from. However, if you look at our characterization circuits, for best performance, we recommend something lower. Much of our characterization data is done with a single tone which gives 333mV p-p out of each side of the DAC. This results in a 235mV RMS swing out of the DAC which ends up being 0.46dB into the 50ohm input of a spectrum analyzer. I think it's most likely that they are not taking into account the 50 ohms of their spectrum analyzer when they are doing the power calculation,

AD9786: Thermal pad connection

Question 1.) Pg 9 - Pin 2 is DNC Pg 47 - Pin 2 is labeled as LPF in the application circuit. 2.) Pg 55 - Must the thermal pad be connected to AGND or DGND? Answer 1) DNC = Do Not Connect My guess is that figure 88, page 47 is a throwback to the fact that we had an on chip PLL clock multiplier (requiring a loop filter) on the original AD9786. (Those who want that feature need to look instead at the AD9779). Therefore please leave pin 2 unconnected. 2) The exposed thermal pad should be connected to DGND, for best DAC performance (noise, distortion).

AD9786: Propagation delay

Question What is the dependency of the propagation delay and settling time of the AD9786? Answer Propogation delay is dependent on mostly digital filter configuration since each filter has its own group delay depending on #of taps (i.e. group delay=FIR Taps/2) . The 1st stage filter dominates since it has the most filter taps and runs at the input data rate. After the digital filter, the data will experience around a 5 clock cycle delay (i.e. relative to DAC CLK) before updating the TxDAC. In terms of output settling time, the TxDAC core settles to 0.1% within 10 nsec. Note, since this device is used for frequency domain sort of applictions, output settling time is not specified nor is an issue since a analog bandlimiting filter follows the DAC which has even a greater settling time.

Question For our application we are using the DAC AD9786 as a straight DAC, that is, with the default settings. We are not using the SPI interface either. We want, however, to Reset the DAC each time the system is reseted. For that we would like to know the minimal details about the timing of the Reset Signal (how long it must stay on, if it is active high), that cannot be found in the Datasheet for this product. Answer A positive pulse with minimum high duration of 10 nsec is required to RESET device.

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AD9786 Not Recommended for New Designs
The AD9786 is the 16-bit member of the latest high-performanceÂ TxDAC+Â® product family. Designed specifically to address multicarrier communications architectures...
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AD9786 on Analog.com