AD9777: DATACLK can only be output pin

Question I found the below description in the datasheet as is shown in attached file. But I can not find any detailed description on the address 02h, Bit 3. I have no idea how to set the bit as either input or output. Would you pls give your professional advice on it? Answer The DATACLK pin can only be an output. The pin description is error, since we do not support DATACLK as an input signal. I would recommend other devices be considered for new designs instead of the AD9777. The AD9779A or the AD9125 are newer devices that should be better alternatives. The AD9777 power consumption and performance is unlikely to be as good as either of the newer devices.

AD9777: Modulating the bandwidth

Question I would like to know if is it possible to use AD9777's Direct-IF option so that DAC signal output would be 100-120 MHz (communication signal bandwidth)? This would be achieved by upconverting 30-50 MHz band with 70 MHz (Direct-IF?) inside DAC. Now I'd like to feed this signal through AD8345 and upconvert it thereby to 900-2820 MHz potential frequency output range. The uncertainty here is, that I'm not sure if AD8345 is able to handle 100-120 MHz input (There was 80 MHz input bandwidth specified in the specs, but does this mean input frequencies from 0 to 80 MHz?) Also I'd like to have or know the spectrum for this 100-120 MHz DAC output, that the filter requirements could be optimised? What is the settling time for AD8345 output when LO is changed from 250 to 1000 MHz in 150 ns? Answer Q1. Can the AD8345 handle a 100-120MHz input? A1. No, the frequency response of the baseband input rolls off before then, as shown in TPC2 on page 5 of the datasheet. This plot also shows that the frequency response depends on the singal amplitude, indicating a slew rate limitation. The 80MHz bandwidth spec means that frequencies from dc to around 80MHz are passed by the baseband input while frequencies >80MHz are attenuated. Q2. What is the output spectrum of the 100MHz to 120MHz output from the DAC? A1. Difficult answer to explain. Basically your filter should eliminate the images caused by the DAC's analog output aliased with the DAC's sampling frequency. The output should ideally consist of your input band of frequencies (0 to 50MHz) translated up in frequency so that the frequency lies between 70MHz and 120MHz. In addition you will have an image band spreading from fs - 120MHZ to fs -70MHz and another band from fs +70MHz to fs + 120MHz and another band from 2fs -120MHz to 2fs -70MHz . You filter has to pass 120MHz, but attenuate fs - 120MHz. However the AD9777 has additional digital filtering to ease the anti-aliasing filter requirements. The AD9777 datasheet contains an excellent explanation of image rejection and complex modulation, from pg 30 on. In addition our seminar on "High Speed Design Techniques" section 4 contains valuable general material on sampled data systems. Q3. Settling time of AD8345 output in response to a step change in LO A3. Although the LO might be subject to a step change in frequency in the case of an agile LO generator, we haven't characterised the settling time in response to such a step change. I think it should be able to follow a 150ns rise time, but I don't know what frequency artefacts might be produced by such a sudden change. You might like to obtain samples/evaluation board ($99) for the AD8345 and evaluate this aspect fo the devices performance yourself.

AD9777 / AD9779: The two channel DACs, can they be used separately?

Question I have two independent real data (for example from two different DUC) to I input port and Q input port respectively of AD9779. The modulation is disabled, I only use two internal DACs to output two independent analog signals. Can the two DACs be used separately likr this? Also I want to know if this set up will function for AD9777 as well. Answer Yes, as long as the modulators in the AD9779 are disabled, the AD9779 can be used as two separate DACs, with independent digital data in and independent analog data out. The modulators in the AD9779 operate in complex mode only, so when the modulators are enabled, the data paths are no longer independent. The AD9777 is slightly different. When you use the modulators in the AD9777, they can be programmed for complex mode, which is similar to the AD9779 modulator mode. The modulators in the AD9777 can also be programmed for real mode, in which case the modulation is done independently for each of the two channels,

What is the latency of the AD9777,5,3 DAC family?

What is the latency of AD9777,AD9775 and AD9773 16,14 and 12 bit DACs? The answer is shown in the table below. AD977X Latency Table Interpolation Rate Modulation Rate Stage 1 Latency Stage 2 Latency Stage 3 Latency Modulator Latency Total Latency 2 1 56 0 0 0 56 2 2 56 0 0 20 76 2 4 56 0 0 22 78 2 8 56 0 0 21 77 4 1 112 34 0 0 146 4 2 112 34 0 20 166 4 4 112 34 0 22 168 4 8 112 34 0 21 167 8 1 224 68 24 0 316 8 2 224 68 24 20 336 8 4 224 68 24 22 338 8 8 224 68 24 21 337 Note: All latencies expressed in multiples of the DAC update rate, f DAC This FAQ was generated from the following discussion: latency of the AD9777,5,3 DAC family

AD9777 max speed and timing query (SR#: 1200982)

Q using AD9777 in 2 port mode on 120 MHz. Data and clock is fed by a FPGA to the DAC. According to the datasheet this should be possible to use 120MHz both with pll enable and disable (read from table 11 in datasheet). But according to the figure 55 data has to be stable tOD+tH6.5ns+3.2ns=9.7ns ie more than a period = 8.33 ns so how could this work.? Then we changed to set the PLL enable. And our problem then is when we use the PLL the data out is not correct. I have pictures of the timing. A At 120Mhz CLKIN the clock period is 8.3333ns as stated below. from reading of figure 55 is that data must be valid for at least 6.5ns. Data needs to go high 5.0ns before DATACLOCK (not CLKIN) goes high. The hold time is -3.2ns meaning that data can go low 3.2ns before DATACLK goes high. DATA can change 5.0ns before DATACLK goes high, then change 8.333ns later and meet the spec. Figure 55 applies to Two Port Mode, PLL disabled.

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The AD9777 is the 16-bit member of a new pin-compatible family of high-speed dual Interpolating TxDAC+® converters with a maximum input data rate of 160...
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