What is the latency of the AD9739?

Q. What is the latency of the AD9739? ----------------------------------------------------------------------------- A. Define the latency, or pipeline delay, as the elapsed time from a sample clocked at the input to the AD9739 until the analog output begins changing. The AD9739 DAC pipeline delay is 78 +/-2 DAC clock cycles. The variable +/-2 is due to the random state of the DCO divider at power up (see Fig 95 in the Rev. A data sheet).

Why do I see a very large signal at 2*fdac for the AD9739 DAC?

Q Why do I see a very large signal at 2*fdac for the AD9739 DAC? It is not clear to me why I see a very large 100mV amplitude signal at 2xfDAC. This corresponds to 3mA switching current. Why is this so large? A Many of our DACs, including the AD9739, use a proprietary DAC switching technique called the quad-switch. This removes code-dependent clock spurs and creates a constant high-energy spur at 2*Fs. In the time-domain, the unfiltered DAC output will have high-energy glitches due to this reason. Since these glitches reside at 2*Fs, the analog filter following the DAC should be able to attenuate them significantly. Note that on products such as the 9707 (which do not use this switching technique), the unfiltered DAC output will look a lot "cleaner" in the time domain.

improve your AD9739's SNR

Do you find the signal integrity of data transfer to your AD9739 DAC isn't quite as perfect as you expect? Odd small temperature ranges in which SNR or BER is worse than expected? Then consider increasing “fine_del_skew” in register 0x13. I'm using the DACs in radios with a circuit close to that in figure 52 of the revC data sheet, and I notice that BER performance is reduced over a narrow temperature range. The actual BER isn't awful, but it goes up several orders of magnitude and then drops back down over about a 5 degree temperature range - unusual behaviour. After some investigation, it appears the DACs are not always acquiring correct data from the FPGA that drives them. The figure below shows measurements of the internal mu-delay value read back from a radio's AD9739 chip while it was exercised in an environmental chamber. The relationship between mu-delay and temperature is fairly linear, but shows some missing codes – eg 3 missing codes near 48 degrees C in this plot. It's near this temperature that the radio misbehaves. (Note the mu-tracking loop doesn't always come up exactly the same from one boot to another, so the temperature that causes the missing codes varies from one boot to another too.) I'm guessing that near the missing-code temperature the mu tracking loop is jumping back-and forth across the wider 4-code gap so there is an extra 36psec timing jitter on DCO. This is in turn reflected back on the DCI from the FPGA. The data receiver controller's tracking loop may fail occasionally to cope with the extra jitter on the DCI and not correctly acquire the data lanes from the FPGA. Hence the odd bad constellation point from the radio. The key to working around this problem appears to be increasing the fine_del_skew value in register 0x13. The data sheet doesn't say much about this parameter, but with it set to 6 rather than the recommended value of 2, my radios work as they should.

Driving the clock of AD9739 DAC

Q I'm using the AD9739 DAC device and according to its datasheet, the best way to drive its clock is by using the ADCLK914 (HVDS) driver. Can I use the ADF4350 to drive the ADCLK914? What is the best way to interface between the RF output of the ADF4350 and the digital input of the ADCLK914 A One can drive the AD9739 directly from the ADF4350 since it has the same CML output structure as the ADCLK914 and provides a "square-wave" like output with sufficient voltage swing when output bias is set to 5.5 dbm output power.

AD9739_R2-EBZ DAC Output stage termination

Q My application requires a wideband, single-ended, 50 Ohm output (20MHz - 2.5GHz). I was thinking to use the output stage as implemented on the evaluation board (AD9739_R2-EBZ EVALUATION BOARD). However, I noticed that the characteristic impedance of the implemented balun (TC1-33-75G2+) is 75 Ohm. A You are right! The AD9739’s output has an impedance of 75ohms and in the Evalboard, this is in parallel with 90ohms on both the negative and positive analog outputs and this implies an output impedance into the transformer of about 50ohms. The Product Expert for this device has confirmed that they looked at this balun over the 1st, 2nd, and 3rd Nyquist zones and it gave the best performance of the baluns in the group they tested. So, they chose this one for the Evalboard. Therefore, the Evalboard setup with the TC1-33-75G2+ will suffice for your 50ohm single-ended output.

AD9739: Output amplitude DC-offset

Q Why is the difference in DC-offset so large between devices? How to avoid? A The DC offset is a result of the balun, MABACT0039, only providing a DC short to the IN pin while the IP pin is connected to a 50 ohm load (as well as 90.9 ohm resistor). We now recommend using a balun (see attached) that has an extra tertiary winding that provides DC short such that both IP and IN remain at 0 V bias. Note,a balun (or transformer) has a lower cut-off frequency hence should only be used for ac applications where reconstructed signal falls within its 1 dB passband. I also attached some more information on the output stage of the AD9739 below. Attachments: AD9739_OutputamplitudeDC-offset2.zip

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