Datasheet errors in the AD9736/5/4

Question Question 1) Is the datasheet 288522419AD9734_5_6_0.pdf the latest version? There seem to be pinout errors on page 54 og 68. Question 2) What connections are reccommended for the 2 unused bits in this 12-bit device? I assume I want to drive DB2 through DB13 with my 12-bit data. Question 3) Must the RESET signal be synchronous with DATACLK_IN, or CLK? What is the required duration of RESET? Answer First off, the schematic of the rev F eval board in the AD9736/5/4 rev 0 datasheet has errors. Several of the pin numbers for the AD9736 are incorrect. I've attached a correct rev F schematic for your reference. The errors in pin numbers are located around the data inputs. I just noticed one other mistake on the AD9736 datasheet. In the correct schematic I have attached, the pins on the AD9736 are called out as LVDS13......to LVDS0. The netlisted pins on the schematic are listed as DB0 to DB13 for these same pins. However, if you look at the pin function description on page 12 of the datasheet, the pins on the AD9736 are referred to as DB13 to DB0, but this bus is reversed with respect to the DB13 to DB0 on the schematic. Maybe you've already noticed this. At the end of the day, the MSB and LSB are in the right order on page 12, pin numbers are also correct on page 12, and the pin numbers are correct on the rev F schematic I've attached to this email. I apologize for the confusion, we've got to fix this. The AD9735 is the 12 bit member of the AD9736 family which includes the 14 bit AD9736, the 12 bit AD9735 and the 10 bit AD9734. However, we only make one eval board and depending on the customer request, we stuff the board with either the 14,12, or 10 bit part. Between the three eval boards, the data bus is always MSB (most significant bit) justified. That is, if you look at the eval board schematic, the pins that are labelled LVDS13N and LVDS13P are the MSB pins (pins K13,K14). These same pins will be the MSB on the AD9735 and on the AD9734. On the AD9735, pins M2,M1,N1,P1 will be no connects, as they would represent the 13th and 14th bits in this TxDAC family. On the AD9734, pins M2,M1,N1,P1,N2,P2,N3,P3 will be no connects, as they would represent the 11th and 12th bits in this TxDAC family. The RESET pin is indeed asynchronous, does not have be coincident with clock. The required duration is no longer than ten DAC clock cylces.

AD9734: Synchronize two DACs

Question We are using two AD9734 DAC's for impementing wideband wireless backhaul modem analog frontend. Two DAC's used for synchronous transmission of two baseband channels. To sync the DAC's we enable FIFO controllers on both chips to monitor FIFOSTAT registers (reg.7 7:6) and change value of PHOF register (reg.7 1:0) to align the DAC's output signal. Our system software performs initial ailgnment of the DAC's output signals during the startup and monitoring of the sync after the startup. During the monitoring of the FIFOSTAT value on the DAC's we observe random variations of the FIFOSTAT value during normal work of the system. This leads our software to show incorrect sync status (we see that DAC's are out of sync but the system works okay) and also not able to recover the system when we really lost the DAC sync. Answer Seems we have resolved our problem with the AD9734 DAC's synchronization. The problem with the change of FIFOSTAT was due to the phase relationship between the DACCLK_IN and DACCLK clock signals. The initial parameters of our design give us the situation that we have phase of the these clock close to each other. This situation leads to incorrect sampling of read FIFO pointer value by the DACCLK clock. We conclude this looking on Figure 82 of AD9734 datasheet the read pointer (signal from DATACLK_IN domain) value is directly sampled by the signal from DACCLK domain. We suppose that due to this things we see changes of the FIFOSTAT values but have the correct synchronization between the DAC's. The issue has been resolved by changing the phase of the DACCLK_IN clock by changing phase of the FPGA PLL clock that is produced from the DACCLK_OUT clock. After changing the clock phase we have stable values from FIFOSTAT on both DAC's and correct synchronization between the DAC's.

AD9734: multichip SYNCHRONIZATION

Question 1, I am using four AD9734s. Because DACCLK is divided by 2 to create DATACLK_OUT, the phase of DATACLK_OUT can be 0° or 180°, it's uncertain. As the red line shown (attache figure 1), the DATACLK_OUT is also used to transit the incoming data to the DACCLK domain. So for multiple AD9734s, even though their DATACLK_INs and DACCLKs have the same phase, because of the Dac Sampling Signal's(Red line) uncertainty of different AD9734s, the sequence of feeding D1A and D2A into DAC CORE is different. So multiple AD9734s' DAC output can't be synchronized, that is, compared to other DAC's output, some DAC' output may lag one DACCLK. 2, Also,I found another problem: after I configured the MODE REGISTER (0x00)and FSC(0x02,0x03), the timings of multiple DAC output may be variable. For example, before writing register, the first three DAC output is good and the fourth DAC output lags one DACLK, but after writing registers, the first two DAC output is OK and the third and fourth DAC output lags one DACCLK. Whether the operation to register can make influence to the DACCLK? Would you please give me some advices about the two problems? Answer The AD9734 has two internal timing domains. The first domain is the digital inputs which are clocked by the DATA_CLK_IN. The second domain is where the DAC actually gets a clock from the DAC_CLK_IN. These domains run independently and there is no required timing relationship (no set up and hold requirement) between the DATACLK_IN and DAC_CLK_IN. The key to the input domain handing off the digital data to the DAC domain is that there is an internal FIFO that automatically makes up for any phase difference between DATACLK_IN and DAC_CLK_IN. The big issue with this is that anytime the DAC powers up, the FIFO can come up in one of several valid different states, all of which cause a different delay from the digital inputs to the DAC output. I'm sure this is why you are seeing the problem. The FIFO can be turned off, but when it is turned off, then there are timing requirements that must be met between DATACLK_IN and DAC_CLK_IN. These timing requirements are given in table 28 on page 55 of the AD9734 rev A datasheet. The solution that we have recommended in the past for synchronizing multiple AD9734s is that a special circuit must be built in the FPGA/digital driver. This circuit takes the DATACLK_OUT from the first AD9734 and uses it to sample the DATACLK_OUT signals from all of the other AD9734s. If it detects that any of the DATACLK_OUT signals are inverted from the first one, then it automatically inverts the DATACLK_IN for that AD9734. In this way, strict timing relationships can be achieved between the DATACLK_OUT, DATACLK_IN and DACCLK on all AD9734s.

Question I'd like a sine wave of 2.375 GHz, so the plan is to generate 375 MHz but as the sample rate is 1 Gsps, the aliases will appear at 625 MHz, 1.375 GHz, 1.625 GHz, 2.375 GHz 2.625 GHz and so on. Can the DACs available achieve these high frequency components, or does something about the devices (output filter, slew rate limited output?) mean that this approach rules out certain parts? Answer The main additional roll-off you will encounter is the R-C time constant of the DAC’s output transistors (big CMOS devices = C) and the load resistance of your system (likely 50 ohms). With the AD9734, it would be tough to get 9 GHz. If you used the AD9129, you could directly synthesize your 2.375 GHz signal using mix-mode and a high clock rate of 2.8 GHz. You’d likely be able to see your 9 GHz signals if you loaded the AD9129 output with 25 ohms or even 12.5 ohms and then transformed it back up to 50 ohms with a 2:1 or 4:1 balun. Check the recently released article on the AD9129 for improved matching and what it did for the output response. http://edn.com/design/analog/4429553/2/Understanding-and-designing-wideband-outp ut-networks-for-high-speed-D-A-converters-

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AD9734 Not Recommended for New Designs
The AD9736, AD9735, and AD9734 are high performance, high frequency DACs that provide sample rates of up to 1200 MSPS, permitting multicarrier generation...
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