AD9148: Unused channel / Unused pins

Question The REFCLK/SYNC input does not need to be used. Can this input be left floating or what termination is otherwise required? Also Port B is not being used, can these inputs be left floating? Answer You can float the REFCLK pins when you drive DACCLK. When you use only one of the two channels, you can float the unused input. For Port B, you just need to tie the Frame inputs to LVDS logic low if you are not using Port B, they can cause problems when you float them.

AD9148-EBZ + SDP-H1 Input Data Rate limitation

Q: AD9148-EBZ + SDP-H1 : What is the maximum frequency possible on OUT1 ? A: AD9148-EBZ+ SDP-H1 can only support to a Max Data Rate(set in DPG Lite) of ~190MHz. AD9148 can produce a higher frequency output but the 190MHz datarate is the limitation on the current evaluation platform (SDP-H1). Higher data rates can be supported by DPG3. RE: AD9148-EBZ + SDP-H1 : What is the maximum frequency possible on OUT1 ?

English

Forums
Popular Forums
Product Forums
View All
Application Forums
Design Center Forums
Learn
Highlighted Webinar

Fast-Track Certification: Leveraging IC Safety App Notes for Functional Safety Designs
Stop guessing, start certifying. Learn how to use IC safety application notes to streamline your FMEDA and meet IEC 61508 and ISO 13849 standards with...
Places
Libraries
Upcoming Learning & Events
View All Webinars
Community Hub
Challenge Yourself!
View All
What's Brewing
View All
Places
Resources
View All
ContentZone
Visit ContentZone
Search content by industry or technology.

Blogs

Technical Articles

Tutorials

Videos

Webinars

Your ADI content all in one place.
View ContentZone
The Latest Read

Clock Tree Design and Why “PLL Locked” Is Not Enough
In high-performance RF systems, clocking architecture is a foundational element that directly governs signal integrity, synchronization, and overall system...

New Release

Signal Chain Designer: DC Error Simulation
This video covers the DC error calculation capabilities of Signal Chain Designer. DC error is unique in that often requires calibration and has so many...

Recent Technical Insights

Improving Industrial Functional Safety Compliance with High Performance Supervisory CircuitsPart 5: Sequencers Eliminate Systematic Failures
This article shifts focus from managing the quantitative metrics of functional safety toward mastering the qualitative yet equally critical challenge:...

EngineerZone

High-Speed DACs

Log In

User
Site
Search

OR

Ask a Question

Data Converters

High-Speed DACs

Documents AD9148: FAQ

Q&A
File Uploads
FAQs/Docs
Members
Tags
Cancel

Products Mentioned

AD9148 Recommended for New Designs
The AD9148 is a quad, 16-bit, high dynamic range, digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS. These devices include features...
Datasheet
AD9148 on Analog.com

Table of Contents

HIGH-SPEED DAC SUPPORT COMMUNITY
+Documents
+AD768ARZ: FAQ
+AD9102: FAQ
+AD9106: FAQ
+AD9115: FAQ
+AD9116: FAQ
+AD9117: FAQ
+AD9119: FAQ
+AD9122: FAQ
+AD9129: FAQ
+AD9135: FAQ
+AD9142A: FAQ
+AD9144: FAQ
+AD9146: FAQ
-AD9148: FAQ
- AD9148-EBZ + SDP-H1 Input Data Rate limitation
- AD9148: Unused channel / Unused pins
+AD9286: FAQ
+AD9712: FAQ
+AD9716: FAQ
+AD9717: FAQ
+AD9726: FAQ
+AD9734: FAQ
+AD9736: FAQ
+AD9739: FAQ
+AD9739A: FAQ
+AD9742: FAQ
+AD9744: FAQ
+AD9747: FAQ
+AD9748: FAQ
+AD974: FAQ
+AD9763: FAQ
+AD9765: FAQ
+AD9767:FAQ
+AD976A: FAQ
+AD9774: FAQ
+AD9776: FAQ
+AD9777: FAQ
+AD9779: FAQ
+AD9779A: FAQ
+AD977: FAQ
+AD977A: FAQ
+AD9780: FAQ
+AD9783: FAQ
+AD9786: FAQ
+AD9788: FAQ
+AD9789: FAQ
+AD9161: FAQ
+AD9162: FAQ
+AD9164: FAQ
+AD9856: FAQ
+AD9857: FAQ
+AD9957: FAQ
+ADV7123: FAQ
+ADV7125: FAQ
+DPG3: FAQ
+MAX5189BEEI+: FAQ
+MAX5190BEEG+: FAQ
+MAX5868: FAQ
+MAX5871EXE+T: FAQ
+MAX5877EGK+D: FAQ
+MAX5880AUXF+: FAQ
+MAX5884EGM: FAQ
+MAX5891EGK+D: FAQ
+AD9136: FAQ
+AD9177: FAQ