tEN_SDIO/tDIS_SDIO : AD9144 Min-Max value

Question AD9144 datasheet does not report value of tEN_SDIO and tDIS_SDIO for supported 3-wire SPI mode (described in AN-877). Is it possible to know themin-max value of those parameters? Answer We could use the tDV to judge when the output data will be available from the falling edge on the output pin. Both of these have similar meaning but a bit different. tDV means how much time the output data will be valid on the SDIO after the falling edge ofSCLK. If the users wants to avoiding driving SDIO after it becomes output, he needs to release the bus prior to the falling edge of SCLK.

What is the max data rate the AD9144 supports?

The AD9144 supports up to 1060MHz usable complex signal bandwidth. This allows customers to generate very wideband signals used in a variety of applications.

What is the highest RF output frequency supported by the AD9144?

The AD9144 has an on-chip NCO that can be used to modulate quadrature input signals up to half the Nyquist rate of the DAC. When running at the maximum DAC update rate of 2.8GSPS this allows customers to output frequencies up to 1.4GHz.

AD9144 - What JESD204B SERDES modes are available on the AD9144?

The AD9144 has 4 DACs and 8 available SERDES lanes with flexible interface configurations to meet various customer needs. The table below shows the transport layer JESD204B link parameters for each mode supported. These parameters are defined per link; all modes listed are supported in single link operation whereas dual link operation is only supported for Mode 4, 5, 6, 7, 9 and 10. Parameter Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 9 Mode 10 M (Converter Counts) 4 4 4 4 2 2 2 2 1 1 L (Lane Counts) 8 8 4 2 4 4 2 1 2 1 S (Samples/Converter/Frame) 1 2 1 1 1 2 1 1 1 1 F (Octets/Frame/Lane) 1 2 2 4 1 2 2 4 1 2 K (Frames/Multiframe) 32 16 or 32 16 or 32 16 or 32 32 16 or 32 16 or 32 16 or 32 32 16 or 32 High-Speed DACs

AD9144 - What is the difference between the DPG3 compatible boards and the FMC evaluation board?

The FMC compatible evaluation board is designed to allow the customer to connect the DAC evaluation board to an FPGA evaluation board of their choosing. This allows the customer to evaluate a specific FPGA along with the DAC in a system-like environment.

AD9144 - What evaluation boards are available?

There are three evaluation boards available for the AD9144: AD9144-EBZ DAC Only Evaluation Board [DPG3 Compatible] AD9144-M6720-EBZ DAC + Modulator (ADRF6720) Evaluation Board [DPG3 Compatible] AD9144-FMC-EBZ DAC Only FMC Evaluation Board [FPGA Compatible] For full listing and pricing, visit AD9144 Evaluation Board | Analog Devices

AD9144 - Is this a JESD204B SERDES high-speed DAC product?

Yes, the AD9144 is a 16-bit 2.8GSPS 8-lane JESD204B SERDES quad high-speed digital-to-analog converter. This is the first high-speed DAC product by ADI that supports the JESD204B serial interface. It provides a high sample rate and input bandwidth for customers along with low noise spectral density for a broad customer base. For more information, visit the product page. AD9144

AD9144 - Does the AD9144 support deterministic latency/multi-chip synchronization?

Yes, the AD9144 supports JESD204B Subclass 0 and Subclass 1 operations for deterministic latency. Subclass 1 provides synchronization to within ½ a DAC clock period and requires a SYSREF ± signal to achieve this latency variation.

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AD9144 Recommended for New Designs
The AD9144 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.8 GSPS, permitting a multicarrier...
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