AD9142A: error message when setting up offsets ( IDAC/QDAC, IQ phase& Gain ADJ )

Question Is it possible to control “ I DAC DC offset and DAC DC offset “ with your GUI? I have got an error message (see below) (IDAC/QDAC, IQ phase& Gain ADJ does not work also) Could you send me a new GUI updated please? Below the error message , I got by changing value of IDAC DC offset Answer Our Product Line Engineers have updated the software to fix this error. You can access the updated software on the Analog Devices wiki at this link: http://wiki.analog.com/resources/eval/dpg/eval-ad9142?

What is the Psi-jt for the AD9142A package (72-pin LFCSP)?

The Psi-jt for the AD9142A package is 0.11C/Watt.

AD9142A Byte Interface Mode

Re-posting this question and there was no response earlier........... I am interested in learning more about the AD9142A byte-interface mode, before evaluating the DAC We plan to use 300MHz DCI clock with x4 interpolation. So the DAC shall be clocked at 1200MHz Fdac. This is the configuration we are planning for the 16-bit interface mode. From the timing diagram for the byte-interface mode shown in the datasheet, the main changes i see is that the IQ data is provided as DDR at DCI clock,with alternating 8-bits of I and Q data. But what is the DCI clocking rate? Will it be twice of what we would use in 16-bit interface mode ? So are we looking at a 600MHz DCI clock with byte-wide interface ? This will exceed the maximum DCI clock limits. Your inputs are appreciated.... Thanks, AB Hi AB, Your understanding is correct. The max DDR data rate AD9142A can support is 575M. You should use word interface mode or decreasing the DAC clock rate. thanks. This document was generated from the following discussion: AD9142A Byte Interface Mode

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AD9142A Recommended for New Designs
The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier...
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AD9142A on Analog.com