Question 1

AD9106 / AD9102 Low-Power DAC and Waveform Generator: FAQs

Accepted Answer

Q1: 
 What is the recommended clock source? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A1: 
 For optimum DAC performance, the clock input signal should be a very low jitter, fast rise time differential signal. The clock receiver generates its own common-mode voltage so the differential pair (CLKP and CLKN) should be AC-coupled. 
 For fixed frequency clock input, a low-jitter LVDS-output temperature-compensated crystal oscillator (TCXO) will work well. Refer to Table 5 of the device datasheets for CLKP and CLKN specifications, and the evaluation board schematic in EVAL-AD910x Wiki Page for the clocking circuit and recommended crystal oscillator part number. 
 If frequency division of the clock input is desired, use AD9514 clock distribution IC for low-jitter performance. Refer to the Clock Input section of the device datasheets for more information. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ1 is generated from the following threads: 
 22815/clock-source-for-ad9102 | 115703/sawtooth-waveform-generation-with-ad9102 | 22866/ad9106-questions | 539279/ad9106-software-and-hardware | 22857/ad9106-ad9102-clock-issue | 22765/ad9106-ebz-input-clock | 22660/ad9106-clocking-and-output-questions | 22708/ad9106-no-spi-startup-after-clock-update 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q2: 
 What is the minimum DAC clock input frequency? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A2: 
 There is no minimum input clock frequency. Any clock rate up to 180MHz will work. For optimum AC performance, the recommended clock frequency f CLK in terms of DAC output frequency f OUT is f CLK &ge; 4 x f OUT . 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ2 is generated from the following threads: 
 22636/about-the-clkin-frequency-of-the-ad9102 | 22495/what-s-the-minimum-input-frequency-for-ad9106-for-generating-10mhz-sine-wave | 22327/ad9106 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q3: 
 What is SPI clock polarity and phase? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A3: 
 SCLK is idle low. It leads with a rising edge and trails with a falling edge. SPI data is sampled on SCLK rising edge and shifted out on the falling edge. This is SPI Mode 0, one of the four SPI modes discussed in Introduction to SPI Interface Analog Dialogue. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ3 is generated from the following threads: 
 23094/ad9102-spi-clock-polarity | 110049/ad9102-spi-communication-clock-polarity-and-phase-fpga 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q4: 
 How can I generate waveforms out of the DAC? Are there any examples of SPI register settings and SRAM data vectors I can try? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A4: 
 There is a proper register write sequence that should be followed before waveforms can be generated out of the DACs. Below is an outline of how to set up SPI communication with AD9106 or AD9102. 
 
 Set initial values of IOs.
 
 RESET - Logic High 
 TRIGGER - Logic High 
 CS - Logic High

Set SPI frequency and mode. Refer to FAQ3. 
 Pulse RESET to logic low then high to reset register values. 
 Proceed with register read or write. Refer to pages 20-21 of AD9102 Rev B datasheet, and pages 21-22 of AD9106 Rev C datasheet.
 
 If loading a pattern from SRAM, write data on SRAM registers first. Refer to page 26 of AD9102 Rev B datasheet, and pages 27-28 of AD9106 Rev C datasheet.
 
 To write data: Enable MEM_ACCESS bit in 0x1E register. Write left-justified data to SRAM registers, 0x6000 to 0x6FFF. Afterward, disable MEM_ACCESS bit. 
 To read data: Enable BUF_READ and MEM_ACCESS bits in 0x1E register. After reading data from SRAM registers, disable BUF_READ and MEM_ACCESS bits.

Write to or read from SPI registers. Update last bits of registers 0x1E (RUN bit) and 0x1D (RAMUPDATE bit) at the end of the write sequence.

Set TRIGGER low to start pattern generation. 
 
 Example SPI register settings and SRAM data vectors can be found in the ADI Mbed repositories below. These are also illustrated in page 32 of AD9106 Rev C datasheet, and page 31 of AD9102 Rev B datasheet 
 
 Program files: https://os.mbed.com/teams/AnalogDevices/code/EVAL-AD910x/ 
 Library files: https://os.mbed.com/teams/AnalogDevices/code/AD910x/ 
 
 The codes in the repositories can be used with the evaluation boards EVAL-AD9106 and EVAL-AD9102 which are designed to work with SDP-K1 , an Mbed-enabled hardware. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ4 is generated from the following threads: 
 22773/ad9102-register-settings-for-qpsk-modulation-using-its-internal-4k-buffer | 28889/need-the-command-format-for-the-ad9106 | 22849/ad9102---trouble-with-dds-mode-and-reading-from-sram | 99729/ad9102-how-set-run-bit-in-pat_status-register | 110441/trigger-for-fpga-and-update-bit-ad9102 | 110692/ad9102-trigger-and-update-bit-0x1d | 23072/ad9102-output-signal | 22929/ad9102-spi-connection-question | 110967/ad9106-when-to-set-ramupdate-and-run-bits | 22645/ad9106-how-to-output-the-waves-that-saved-in-the-sram-of-ad9106/399897#399897 | 22720/about-the-function-of-ad9102 | 22520/ad9102-help-with-generator-random-waveform | 106990/sinewave-from-ram-with-ad9102 | 22921/ad9106-sram-read-write | 22668/ad9106-how-to-generate-amplitude-modulated-sine-waves | 22664/for-ad9106-how-to-output-sine-single-with-amplitude-modulated | 22625/ad9106-sine-output-and-tuning-words | 72635/signal-generation-with-ad9106 | 103558/ad9102-dac-constant-gain-offset 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q5: 
 How much does trigger to output delay vary? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A5: 
 Trigger to output delay is t SU plus t DLY as shown in Figure 41 of AD9106 Rev C datasheet (Figure 39 of AD9102 Rev B datasheet) is 96ns for a DAC clock frequency of 180MHz. 
 t SU is the duration between the first rising edge of the clock signal encountered after trigger falling edge. Its minimum values are indicated in Digital Specifications Tables in the datasheet. It should be less than one clock period. 
 t DLY is the duration between the first rising edge of the clock signal encountered after trigger falling edge and start of pattern generation, it can be programmed in the PATTERN_DELAY register. Minimum value is 0x000E. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ5 is generated from the following threads: 
 115781/ad9102-ad9106-delay-between-trigger-and-start-of-generation-from-ram | 22935/ad9102-help-with-trigger-programming/90506#90506 | 22941/ad9106-a-bunch-of-questions 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q6: 
 Is it possible to synchronize multiple AD9102 or AD9106 DACs? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A6: 
 To synchronize multiple AD9102 or AD9106 DACs, tie the /Trigger pins together. For finer trigger to output delay, consider clock synchronization, and t SU and t DELAY as described in FAQ5. 
 See this article for more details on synchronization of multiple AD9102 or AD9106 DACs: Unlocking the Potential of Open-Source Evaluation Platforms for Prototyping Ultrasound Transmit Subsystems | Analog Devices 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ6 is generated from the following threads: 
 536450/ad9102-6---synch-multiple-dds/391549?focus=true#391549 | 22681/ad9106-waveform-synchronisation 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q7: 
 What is SRAM size, word length, and data format? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A7: 
 There are 4096 addresses, 0x6000 to 0x6FFF in the on-chip SRAM. Word length is 14 bits for AD9102, and 12 bits for AD9106. For AD9102 data should be written in bits [15:2] and for AD9106 in bits [15:4] of each SRAM address. 
 SRAM data format or code follows the two&rsquo;s complement notation and is left justified. 14-bit code should be shifted left by 2 bits before writing it to AD9102 SRAM while 12-bit code should be shifted left by 4 bits before writing it to AD9106 SRAM. Alternatively, 14-bit data shifted left by 2 bits can be written to AD9106 SRAM but the last two bits will be truncated. Refer to the table below for equivalent current outputs of some input codes.

14-bit DAC Input Code (Base 10)

AD9102 SRAM Data (Base 16)

12-bit DAC Input Code (Base 10)

AD9106 SRAM Data (Base 16)

I OUTxP

I OUTxN

8191

0x7FFC

2047

0x7FF0

I OUTFS - 1LSB

0

0x0000

0

0x0000

I OUTFS /2

-8192

0x8000

-2048

0x8000

0

I OUTFS -1LSB

Select SRAM as input to a DAC channel by setting WAVE_SELx bits to 0b00 in the following WAV_CONFIG registers: 
 
 For AD9102: Register 0x27 [1:0] 
 For AD9106:
 
 Register 0x27 [1:0] for Channel 1 
 Register 0x27 [9:8] for Channel 2 
 Register 0x26 [1:0] for Channel 3 
 Register 0x26 [9:8] for Channel 4

Refer to FAQ10 for more information on generating data vectors. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ7 is generated from the following threads: 
 105661/ad9102-sram-changes-while-running | 22919/ad9102-sram-data | 109305/ad9102-triangle-wave-with-78-125-khz | 104301/bit-memory-pattern-on-ad9106 | 103558/ad9102-dac-constant-gain-offset 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q8: 
 How can double SPI data write to AD9102 SRAM work? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A8: 
 AD9102 does not have double SPI data write to SRAM feature that AD9106 has. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ 8 is generated from the following threads: 
 22912/ad9102-double-data-spi-mode | 22860/doube-spi-data-line-not-working-on-ad9102 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q9: 
 Does the SRAM address auto-decrement for consecutive SPI read or write operations? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A9: 
 For consecutive write operations in the SRAM address space, the SPI port automatically decrements the register address if CS stays low beyond the first data-word. The start of the auto-decrement write does not necessarily have to be 0x6FFF (can be anywhere between 0x6FFF to 0x6000). Unfortunately, this auto-decrement feature does not apply to consecutive read operations from the SRAM. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ9 is generated from the following threads: 
 22838/ad9106-sram | 537164/ad9102-sram-read-write 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q10: 
 How can I use the on-chip SRAM for arbitrary pattern generation? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A10: 
 Data vector of any waveform shape can be written to the on-chip SRAM but creating the vector can be challenging and time consuming. It will be more convenient to use DPG Lite . Shown below are the waveforms that can be generated using the software. 
 
 When creating data vectors for AD9106 and AD9102, make sure to choose the proper DAC resolution and leave the Unsigned Data box unchecked. A continuous wave vector with record length of 4096 can be created but the SRAM can also be composed of different types of waveforms like in the example below where there are 3 vectors with combined record length of 4096. These can be saved as text files and integrated into the application software. 
 
 It is not required to write to all 4096 addresses. Each DAC channel can fetch data from a fixed SRAM address to another. The start and stop addresses can be set using the following registers: 
 
 For AD9102: Registers 0x5D and 0x5E 
 For AD9106:
 
 Registers 0x5D and 0x5E for Channel 1 
 Registers 0x59 and 0x5A for Channel 2 
 Registers 0x55 and 0x56 for Channel 3 
 Registers 0x51 and 0x52 for Channel 4

------------------------------------------------------------------------------------------------------------------------------ 
 FAQ10 is generated from the following threads: 
 166167/how-to-use-sram-to-output-arbitrary-wave/375798#375798 | 23024/ad9102-output-sweeping-sine-wave | 23009/ad9102-dds---arbitrary-waveform-generation | 22928/awg-using-the-ad9102 | 22833/ad9102-6-frequency-change | 22539/ad9106-ebz | 23025/ad9106-as-a-pulse-generator | 109232/ad9106-and-white-noise | 22981/ad9106-termination-to-avdd-or-gnd-phase-shift-square-wave 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q11: 
 What is the maximum value and resolution of R SET ? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A11: 
 Based on the DC specifications tables in the datasheets, maximum full-scale output current I OUTxFS is 8mA and minimum is 2mA. Following the formula in the DAC Transfer Function section of the datasheets, I OUTxFS = 32 x (V REFIO /R SETx ) , to set I OUTxFS to 8mA with a V REFIO of 1V, an R SETx of 4K&Omega; should be connected to the FSADJx pin of the DAC. Also, to set I OUTxFS to 2mA, R SETx should be 16K&Omega;, the maximum resistor value. 
 If DACx_RSET_EN bit of the FSADJx register is enabled and the on-chip resistors are used for I OUTxFS tuning, bits [4:0] of the same register can be used to set the on-chip resistor value. Refer to the table of values below. The maximum DACx_RSET value is 0x14 and minimum is 0x05 denoting a resolution of 800&Omega;.

R SETx ( &Omega;)

I OUTxFS (mA), V REFIO = 1V

DACx_RSET (Bits [4:0] of FSADJx register)

4000

8

0x05

8000

4

0x0A (default)

16000

2

0x14

On-chip R SETx values can be set using the following registers: 
 
 For AD9102: Register 0x0C 
 For AD9106:
 
 Register 0x0C for Channel 1 
 Register 0x0B for Channel 2 
 Register 0x0A for Channel 3 
 Register 0x09 for Channel 4

------------------------------------------------------------------------------------------------------------------------------ 
 FAQ11 is generated from the following threads: 
 22542/ad9106-internal-rset-range-and-values | 22731/internal-rset-values/138634#138634 | 22389/ad9106-full-scale-output-current | 22979/ad9106-minimum-hardware-set 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q12: 
 Why does automatic I OUTFS calibration result to an overflow or underflow? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A12: 
 Automatic I OUTFS calibration may result to an overflow or underflow if the hardware setup and step-by-step procedure described in pages 23-24 of AD9106 Rev C datasheet (pages 22-23 of AD9102 Rev B datasheet) are not followed correctly. Automatic calibration only works when on-chip resistors R SETx are used for I OUTxFS tuning and has a very small effect in gain adjustment. 
 Default clock divider value for the calibration clock is 512 but it can also be set to the values in the table below:

CAL_CLK_DIV - Register 0x0D [2:0] base10

Exponent of 2

CLK Divider

0

2

4

1

3

8

2

4

16

3

5

32

4

6

64

5

7

128

6

8

256

7

9

512 (default)

------------------------------------------------------------------------------------------------------------------------------ 
 FAQ12 is generated from the following threads: 
 164308/ad9106-cal_clk_div-and-bgdr-bits | 22736/underflow-during-ioutfs-calibration | 22866/ad9106-questions | 22893/ad9106 | 22839/ad9106-calibration | 22545/ad9102-calibration-overflow-always 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q13: 
 What is the gain drift with temperature when off-chip/external voltage reference is used? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A13: 
 Gain temperature drift specification does not include effects of the on-chip/internal reference REFIO temperature drift because the ideal gain is calculated using the measured V REFIO . So even with a perfect off-chip/external voltage reference, gain drift will still be around 220 to 250 ppm/&deg;C. Internal reference temperature drift specification is provided separately. Actual values are in the DC Specifications tables in both AD9102 and AD9106 datasheets. Using an off-chip voltage reference with low temperature drift and using off-chip temperature-tracking R SET resistors may result in lower full-scale output drift than using the on-chip options. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ13 is generated from the following threads: 
 111847/ad9106---thermal-drift | 22990/ad9106-external-vref-gain-drift 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q14: 
 How is DACx_DGAIN configured? How does it affect the DAC output waveform? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A14: 
 DACx_DGAIN or digital gain multiplies the digital data at a DAC channel input path by gain values that ranges from -2 to +2. It follows two&rsquo;s complement notation. See example gain values and corresponding 12-bit code in the table below.

Gain

DACx_DGAIN [15:4]

+1

0x400

+2

0x7FF

-1

0xC00

-2

0x800

Although the digital data can be multiplied by up to a magnitude of 2, the DAC current output is limited to the range 0 to I OUTxFS . If the resulting DAC input code, (digital data x digital gain) + offset , exceeds full scale, output will be clipped at I OUTxFS . If code is lower than negative full scale, output will be clipped at 0A. 
 Digital gain can be set using the following registers: 
 
 0x35 for AD9102, 
 0x35, 0x34, 0x33, 0x32 for AD9106 Channels 1 to 4, respectively. 
 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ14 is generated from the following threads: 
 22962/setting-ad9102-output-amplitude | 90355/ad9102-dac-datapaths-function | 22663/for-ad9106-how-to-configure-the-dac4_gain-dac4_dig_gain-register | 533522/ad9106-gain-setting-question/405239#405239 | 22972/ad9106-errata 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q15: 
 How can I use DDSx_PW register for phase adjustment? Can I use it to offset phase of SRAM-generated waveform? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A15: 
 DDSx_PW register or DDSx phase offset register can be used to adjust phase offset of a DDS-generated waveform only. It will not affect other prestored waveforms and SRAM-generated waveform. DDSx_PW is 16 bits wide and corresponds to up to 360 degrees of phase offset. Resolution is around 0.055 degrees. 
 Select DDS pattern generator as input to a DAC channel by choosing prestored waveform and DDS output in the following WAV_CONFIG registers: 
 
 0x27 [5:0] for AD9102, 
 0x27 [5:0], 0x27 [13:8], 0x26 [5:0], 0x26 [13:8] for AD9106 Channels 1 to 4, respectively. 
 
 DDS waveform phase offset can be adjusted using the following registers: 
 
 0x43 for AD9102, 
 0x43, 0x42, 0x41, 0x40 for AD9106 Channels 1 to 4, respectively. 
 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ15 is generated from the following threads: 
 22968/questions-regarding-ad9102-trigger-signal | 22566/about-ad9102-phase | 22975/ad6102-phase-adjustment/79867#79867 | 141267/initialization-of-ad9106/366030#366030 | 22941/ad9106-a-bunch-of-questions 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q16: 
 What is the resolution of the DAC constant? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A16: 
 AD9106 and AD9102 can output a DC signal by selecting prestored waveform and constant value in the following registers: 
 
 For AD9102: Register 0x27 [5:0] 
 For AD9106:
 
 Register 0x27 [5:0] for Channel 1 
 Register 0x27 [13:8] for Channel 2 
 Register 0x26 [5:0] for Channel 3 
 Register 0x26 [13:8] for Channel 4

The DAC constant value, like SRAM data, follows the two&rsquo;s complement notation. It is 12-bits wide and can be set in bits [15:4] of the DACx_CST registers in the following addresses: 
 
 0x31 for AD9102, 
 0x31, 0x30, 0x2F, 0x2E for AD9106 Channels 1 to 4, respectively. 
 
 In the table below are equivalent current outputs of some input codes.

14-bit DAC Input Code (Base 10)

DACx_CST Register (Base 16)

I OUTxP

I OUTxN

2047

0x7FF

I OUTFS - 1LSB

0

0x000

I OUTFS /2

-2048

0x800

0

I OUTFS -1LSB

------------------------------------------------------------------------------------------------------------------------------ 
 FAQ 16 is generated from the following threads: 
 22537/digital-gain-in-ad9106-does-not-seem-to-have-an-effect | 22922/ad9102-configuration-register-values 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q17: 
 How can I generate sawtooth waveforms and how do I determine the sawtooth frequency? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A17: 
 To generate sawtooth or triangle waveforms using the on-chip sawtooth pattern generator, select it first as input to a DAC channel by choosing prestored waveform and sawtooth in the following registers: 
 
 For AD9102: Register 0x27 [5:0] 
 For AD9105:
 
 Register 0x27 [5:0] for Channel 1 
 Register 0x27 [13:8] for Channel 2 
 Register 0x26 [5:0] for Channel 3 
 Register 0x26 [13:8] for Channel 4

Select desired type of sawtooth waveform (ramp up, ramp down, or triangle) and set number of samples per step using the following SAW_CONFIG registers: 
 
 For AD9102: Register 0x37 [7:0] 
 For AD9106:
 
 Register 0x37 [7:0] for Channel 1 
 Register 0x37 [15:8], for Channel 2 
 Register 0x36 [7:0] for Channel 3 
 Register 0x36 [15:8] for Channel 4

Alternatively, sawtooth waveforms can be generated using the on-chip SRAM. Refer to FAQ10. 
 The equation for calculating the sawtooth frequency is below, which is determined by the type of sawtooth (SAW_TYPE), the number of samples per step (SAW_STEP), and the DAC clock frequency. The number of steps of the sawtooth waveform for both AD9102 and AD9106 is 2 14 or 16,384 for either a ramp-up or ramp-down sawtooth (twice as many steps for a triangular waveform). 
 The Pattern Period of a waveform is determined by three things: PAT_PERIOD (Register 0x29), the DAC clock period ( T CLK ), and PAT_PERIOD_BASE (Register 0x28 [7:4]). To make the sawtooth waveform appear as a periodic output without gaps in between each sawtooth, the Waveform Pattern Period (which can be manually adjusted) must be equal to the Sawtooth Pattern Period (which is determined by the sawtooth parameters, SAW_TYPE and SAW_STEP, and the DAC clock frequency). Note that the Sawtooth Pattern Period is not the same as Sawtooth Ramp Time (the Sawtooth Pattern period is the ratio of the Sawtooth Ramp Time and PAT_PERIOD_BASE). 
 
 Sawtooth Frequency = 1 / Sawtooth Ramp Time 
 Sawtooth Ramp Time = N * 2 14 * T CLK * SAW_STEP , where:
 
 N = 1 for positive sawtooth (Ramp-up) or negative sawtooth (Ramp-down) 
 N = 2 for Triangular sawtooth

Sawtooth Pattern Period = Sawtooth Ramp Time / PAT_PERIOD_BASE 
 Waveform Pattern Period = PAT_PERIOD * (PAT_PERIOD_BASE * T CLK ) 
 
 Below are example register configurations and the resulting sawtooth waveforms for DAC clock frequency of 180MHz (T CLK = 5.56ns):

SAW_TYPE

PAT_PERIOD_BASE base10

SAW_STEP

Sawtooth Ramp Time

Sawtooth Pattern Period

Sawtooth Frequency

PAT_PERIOD

Waveform Pattern Period

Waveform

Ramp-down

1

91.02 us

10.986 kHz

0xFFFF

364.08 us

a

Triangular

1

2

364.08 us

2.746 kHz

0xFFFF

364.08 us

b

Ramp-up

8

24

2.185 ms

273.06 us

457.76 Hz

0xC000

273.06 us 
 
 c

Ramp-down

2

1

91.02 us

45.51 us

10.986 kHz

0x2800

113.77 us

d

In the sawtooth waveform examples, Waveform B and Waveform C have the configured Pattern Period equal to the Sawtooth Pattern Period, making the sawtooth waveform look periodic (without any gaps). Meanwhile in Waveform A and Waveform D, the configured Pattern Period is larger than the Sawtooth Pattern Period, producing gaps in between each sawtooth. 
 a. b. 
 c. d. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ17 is generated from the following threads: 
 109305/ad9102-triangle-wave-with-78-125-khz/ | 97981/how-can-i-adjust-the-ad9102-sawtooth-output-frequency | 97979/sawtooth-problem | 22578/ad9102-high-speed-signal-generation-issues | 22744/ad9106-sawtooth-frequency-range-as-function-of-clk/136436#136436 | 90371/ad9106-sawtooth | 90428/ad9106-sawtooth-speed | 22448/sawtooth-waveform-generation-of-5khz-using-dds-ad9106/184421#184421 | 90370/what-is-the-fastest-sawtooth-wave-the-ad9106-can-put-out/201362#201362 
 ------------------------------------------------------------------------------------------------------------------------------ 
 Q18: 
 What is the state of the DAC outputs on power up? 
 ------------------------------------------------------------------------------------------------------------------------------ 
 A18: 
 On power up and with proper load resistors connected, the DAC outputs I OUTxP and I OUTxN go to midrange or I OUTxFS /2. This is also the case when the DACs are idle &ndash; before and after pattern generation. 
 To save power before and after pattern generation, the DACs can be put to sleep by setting bits [3:0] of the POWERCONFIG 0x01 register to 0b1111. 
 ------------------------------------------------------------------------------------------------------------------------------ 
 FAQ 18 is generated from the following threads: 
 22619/ad9106-output-state-on-power-up | 119839/ad9102-output-going-to-midrange-after-pattern-period-executed | 90365/ad9102-dac-output-state-in-sleep-mode 
 ------------------------------------------------------------------------------------------------------------------------------

Question 2

What is the tuning resolution of the output frequency of these devices?

Accepted Answer

Q 
 What is the tuning resolution of the output frequency of these devices? 
 
 A 
 The devices feature a 24-bit frequency tuning word which results in a resolution of 10.8 Hz/LSB with a 180 MHz sampling clock.

Question 3

Digital Pattern Generator?

Accepted Answer

Q 
 Does the evaluation board require a Digital Pattern Generator? 
 
 A 
 No.The AD9102 and AD9106 evaluation hardware requires only a PC with USB connection and a clock source such as a signal generator.

Popular Forums

Product Forums

Application Forums

Design Center Forums

Highlighted Webinar

Places

Libraries

Upcoming Learning & Events

Challenge Yourself!

What's Brewing

Places

Resources

Visit ContentZone

The Latest Read

New Release

Recent Technical Insights

Products Mentioned

AD9102: FAQ