Hi all,
I'm working on the spi communication between AD9106 Evaluation board and TI ezdsp f28335. The AD9106 Evaluation board was tested by using the Labview and demo examples and it also produced the expected waveforms which were the same as the figures shown in the user guide. Then I want to use my own dsp controller f28335 to replace the on-board controller. After checking the schematic of AD9106 EBZ, there have some places need to be modified in hardware:
1. Disconnect the SPI connection between AD9106 and on-board chip PIC18F4550 by removing xjp5,xjp1,xjp3,xjp4 and then get connection from f28335.
2. Disconnect pin2 and pin3 of jp1, then to get a control signal from f28335 for TRIGGERB.
3. Since the voltage level of AVDD, CVDD and DVDD are controlled by three pins of PIC18F4550, and the default voltage of AVDD is 1.8V. By swapping R37 and R38, it makes the initial value of AVDD equals to 3.3V.
That's all the modification I made. Then I followed the recommended sequence of command, writing the codes attached at the end which are exactly the same as example 4 from evaluation board suite.
I'm aware of the importance of two registers PAT_STATUS and RAMUPDATE. The former one is used to set the RUN bit for pattern generation, the latter one is to update all the registers. After sending the all of commands, a falling edge of the trigger terminal is required to generate the waveform.
Please find the waveform of SPI I got:
https://www.dropbox.com/s/bxsfqne96a0ng1a/SPI.JPG
https://www.dropbox.com/s/rcj0zb14u39y5tg/SPI2.JPG
They are waveform of command data, clock signal and cs signal separately from up to down .
Actually, I tested the SPI communication with DAC tlv5604, it works well. However, I still can't get the expected waveform from AD9106. Please help me to check it, I'm stuck in it now. Many thanks
Haimeng
| signal_gen_control (SPICONFIG,0x0000); | ||
| signal_gen_control (POWERCONFIG,0x0E00); | ||
| signal_gen_control (CLOCKCONFIG,0x0000); | ||
| signal_gen_control (REFADJ,0x0000); | ||
| signal_gen_control (DAC4AGAIN,0x4000); | ||
| signal_gen_control (DAC3AGAIN,0x4000); | ||
| signal_gen_control (DAC2AGAIN,0x4000); | ||
| signal_gen_control (DAC1AGAIN,0x4000); | ||
| signal_gen_control (DACxRANGE,0x0000); | ||
| signal_gen_control (FSADJ4,0x1F00); | ||
| signal_gen_control (FSADJ3,0x1F00); | ||
| signal_gen_control (FSADJ2,0x1F00); | ||
| signal_gen_control (FSADJ1,0x1F00); | ||
| signal_gen_control (CALCONFIG,0x0000); | ||
| signal_gen_control (COMPOFFSET,0x0000); |
| signal_gen_control (0x0F,0x0000); | ||
| signal_gen_control (0x10,0x0000); | ||
| signal_gen_control (0x11,0x0000); | ||
| signal_gen_control (0x12,0x0000); | ||
| signal_gen_control (0x13,0x0000); | ||
| signal_gen_control (0x14,0x0000); | ||
| signal_gen_control (0x15,0x0000); | ||
| signal_gen_control (0x16,0x0000); | ||
| signal_gen_control (0x17,0x0000); | ||
| signal_gen_control (0x18,0x0000); | ||
| signal_gen_control (0x19,0x0000); | ||
| signal_gen_control (0x1A,0x0000); | ||
| signal_gen_control (0x1B,0x0000); | ||
| signal_gen_control (0x1C,0x0000); |
| signal_gen_control (RAMUPDATE,0x0000); | ||
| signal_gen_control (PAT_TYPE,0x0000); | ||
| // | signal_gen_control (PAT_STATUS,0x0000); |
| signal_gen_control (PATTERN_DLY,0x000E); | ||
| signal_gen_control (0x21,0x0000); | ||
| signal_gen_control (0x22,0x0000); | ||
| signal_gen_control (0x23,0x0000); |
| signal_gen_control (DAC2DOF,0x0000); | ||
| signal_gen_control (DAC1DOF,0x0000); | ||
| signal_gen_control (WAV4_3CONFIG,0x1212); | ||
| signal_gen_control (WAV2_1CONFIG,0x1232); | ||
| signal_gen_control (PAT_TIMEBASE,0x0111); | ||
| signal_gen_control (PAT_PERIOD,0xFFFF); | ||
| signal_gen_control (DAC4_3PATx,0x0101); | ||
| signal_gen_control (DAC2_1PATx,0x0101); | ||
| signal_gen_control (DOUT_START_DLY,0x0003); | ||
| signal_gen_control (0x2D,0x0000); |
| signal_gen_control (DAC4_CST,0x0000); | ||
| signal_gen_control (DAC3_CST,0x0000); | ||
| signal_gen_control (DAC2_CST,0x0000); | ||
| signal_gen_control (DAC1_CST,0x0000); | ||
| signal_gen_control (DAC4_DGAIN,0x4000); | ||
| signal_gen_control (DAC3_DGAIN,0x4000); | ||
| signal_gen_control (DAC2_DGAIN,0x4000); | ||
| signal_gen_control (DAC1_DGAIN,0x4000); |
| signal_gen_control (SAW4_3CONFIG,0x1011); | ||
| signal_gen_control (SAW2_1CONFIG,0x0600); |
| signal_gen_control (0x38,0x0000); | ||
| signal_gen_control (0x39,0x0000); | ||
| signal_gen_control (0x3A,0x0000); | ||
| signal_gen_control (0x3B,0x0000); | ||
| signal_gen_control (0x3C,0x0000); | ||
| signal_gen_control (0x3D,0x0000); |
| signal_gen_control (DDS_TW32,0x1999); | ||
| signal_gen_control (DDS_TW1,0x9A00); | ||
| signal_gen_control (DDS4_PW,0x0000); | ||
| signal_gen_control (DDS3_PW,0x0000); | ||
| signal_gen_control (DDS2_PW,0x0000); | ||
| signal_gen_control (DDS1_PW,0x0000); | ||
| signal_gen_control (TRIG_TW_SEL,0x0000); |
| signal_gen_control (0x45,0x0000); | ||
| signal_gen_control (0x46,0x0000); | ||
| signal_gen_control (0x47,0x0000); | ||
| signal_gen_control (0x48,0x0000); | ||
| signal_gen_control (0x49,0x0000); | ||
| signal_gen_control (0x4A,0x0000); | ||
| signal_gen_control (0x4B,0x0000); | ||
| signal_gen_control (0x4C,0x0000); | ||
| signal_gen_control (0x4D,0x0000); | ||
| signal_gen_control (0x4E,0x0000); | ||
| signal_gen_control (0x4F,0x0000); |
| signal_gen_control (START_DLY4,0x07D0); | ||
| signal_gen_control (START_ADDR4,0x0000); | ||
| signal_gen_control (STOP_ADDR4,0x0000); | ||
| signal_gen_control (DDS_CYC4 ,0x0001); | ||
| signal_gen_control (START_DLY3,0x03E8); | ||
| signal_gen_control (START_ADDR3,0x0000); | ||
| signal_gen_control (STOP_ADDR3,0x0000); | ||
| signal_gen_control (DDS_CYC3 ,0x0001); | ||
| signal_gen_control (START_DLY2,0x03E8); | ||
| signal_gen_control (START_ADDR2,0x0000); | ||
| signal_gen_control (STOP_ADDR2,0x0000); | ||
| signal_gen_control (DDS_CYC2 ,0x0001); | ||
| signal_gen_control (START_DLY1,0x0FA0); | ||
| signal_gen_control (START_ADDR1,0x0000); | ||
| signal_gen_control (STOP_ADDR1,0x0000); | ||
| signal_gen_control (DDS_CYC1 ,0x16FF); |
| signal_gen_control (PAT_STATUS,0x0001); | ||
| signal_gen_control (RAMUPDATE,0x0001); |
RE: SPI communication issue between AD9106 EBZ and TI ezdsp f28335 by Haimeng:
I have already found the problem is caused by the setting of clock phase.
