AD9162-FMC-EBZ on ZCU102, can't get all CGS to pass

Hi all,

I'm working on establishing the following JESD204B link using AD9162 on ZCU102, since 1 month now:

Lanes: 8

DAC Rate: 4915.2 MHz (using a clean external 122.8 MHz clock and the on borad ADF4533)

Interpolation: x16

Subclass: 0

Lane Rate: 1.536 Gbps per lane (12.288 Gbps total)

The JESDPHY PLL ref clock and tx_core_clk in the FPGA design uses the clock coming from the HPC1 port, which is at 307.2 MHz (thanks to the dividers at the ADF4533 output).

On the software side, I have a bare-metal app which does the following:

- Configure ADF4533 and the clock divider

- Configure the JESD core, perform reset then check PLL lock status

- AD9162 DAC Start-up sequence

- AD9162 JESD204 Start-up sequence from the data sheet

Registers 0x470 and 0x471 gives the following outputs:

- 0x470 : 0xBB, as an example (it changes every time I power cycle the system. It can be any mix of lanes but never ALL of them, 0xFF)

- 0x471 : 0xFF, this one is much more reliable, I can get Frame Sync for all lane often.

I also have some Bad Disparity errors, which are located on the failing CGS lanes( not all the time but still relevant I think);

In the FPGA I observe the following behaviour:

Basically, the SYNC pulse is up for multiple multiframe and drops down at some point. Here is a zoom:

It seems to be pretty constant. After 16 multiframes, the SYNC pulse drops down to low.

I'm looking for ideas at that point. I double checked all registers and clocks. Also strange, it works on a much older version of the design based on Kintex Ultrascale. So I do think my AD9162 is alright.

Any helps would be much appreciated.

Regards,

JB

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