I'm working on establishing the following JESD204B link using AD9162 on ZCU102, since 1 month now:
DAC Rate: 4915.2 MHz (using a clean external 122.8 MHz clock and the on borad ADF4533)
Lane Rate: 1.536 Gbps per lane (12.288 Gbps total)
The JESDPHY PLL ref clock and tx_core_clk in the FPGA design uses the clock coming from the HPC1 port, which is at 307.2 MHz (thanks to the dividers at the ADF4533 output).
On the software side, I have a bare-metal app which does the following:
- Configure ADF4533 and the clock divider
- Configure the JESD core, perform reset then check PLL lock status
- AD9162 DAC Start-up sequence
- AD9162 JESD204 Start-up sequence from the data sheet
Registers 0x470 and 0x471 gives the following outputs:
- 0x470 : 0xBB, as an example (it changes every time I power cycle the system. It can be any mix of lanes but never ALL of them, 0xFF)
- 0x471 : 0xFF, this one is much more reliable, I can get Frame Sync for all lane often.
I also have some Bad Disparity errors, which are located on the failing CGS lanes( not all the time but still relevant I think);
In the FPGA I observe the following behaviour:
Basically, the SYNC pulse is up for multiple multiframe and drops down at some point. Here is a zoom:
It seems to be pretty constant. After 16 multiframes, the SYNC pulse drops down to low.
I'm looking for ideas at that point. I double checked all registers and clocks. Also strange, it works on a much older version of the design based on Kintex Ultrascale. So I do think my AD9162 is alright.
Any helps would be much appreciated.
I need to repeat what jjxia has suggested below:
"have you tried to use ACE to see if it works?". You can simply use ACE to program the DAC eval board and see if JESD link is up and running with ACE configuration. Please let us know how your experiment is going.
Hi and thanks for replying. Using ACE was useful to validate the SPI registers values (and validate that my AD9162 is working correctly) for my bare-metal code. However, it didn't fix the issue. The problem was on the FPGA side of things. It will seem obvious maybe for many people but for a starter like me, the meaning from Xilinx point of view of Line Rate wasn't clear. Turns out that Line rate is the equivalent of Lane Rate, aka the data rate of a single lane. Not the total of all lanes. Fixing this configuration parameter and replicating the SPI registers values outputted by the ACE software, fixed everything.
Also, another tip that I learned the hard way: - It is important that the JESD cores in the FPGA stays in Reset until a valid clock is provided. One can do that using an MMCM and using the "locked" output signal to control the reset.
I tested it on Vivado 2017.4 and 2018.2. JESD core 7.2 and JESD PHY 4.0. Now that I got this working, if any one has questions, I will be happy to help.
Would you mind going into a little more detail about how your clocks are set up? I think I am having an issue with clocks.