I encountered a problem when I used the AD9776A. In my design, the reference clock was 120Mhz, the ADC clock was 480Mhz, the VCO clock was 1920M and the PLL display was locked. I use 15Mhz sine wave and cosine wave as input signal, my input data rate is 120Mhz, the TXENABLE signal keeps high level and the SYNC signal keeps low level, but there is no signal in the output part. Which part should I check? Here is the value of my register.
Assumed this question was resolved outside of this forum.
Is the output that you are expecting from the DAC output or there are some middle components which take the signal from the DAC and pass it to the output?There are number of questions that I have regarding this design. However, this looks to me to be a custom board design. If I guessed it right, then it would be better for you to contact one of our local Field Application Engineers to help you narrow down the problem.