I am using AD9129 at 2457.6 MHz. I get PLL and DLL lock properly. My fifo levels are stable at following values:
address 0x13 is at 0x01
address 0x14 is at 0x01
address 0x15 is at 0x03
address 0x16 is at 0x03.
I am using SED feature of the IC and I am getting no errors at all. My DCI line is another data line, specifically an LVDS line. However when I read register 0x0E I read 0x87 which means data is sampled on incorrect phase.
Why am I getting this error when everything looks just fine?
Secondly, can you please elaborate on what data is sampled on incorrect phase mean and how the IC knows about it?
The question is are you getting output at all or not?
The SED test is used mostly to determine correct connectivity (opens/shorts) for the DAC. For timing errors, you need to use the data receiver status registers. have you verified timing is shifted between the data lines and the DCI when you shift the odelay?