I want to use the AD9163 in 1.3V mode (overclocked) to the VDDx (as described on the top of page 5)
In the datasheet the requirement is for -/+2% for this voltage.
1. what is the load change that the LDO will see from the DAC ? I need it to select the required "load regulation" spec for my LDO.
2. If I use the 1.3V for the serdes as mentioned, give that my FPGA's serdes is 1.2V , is this ok or will there be a problem? if so, what do u recommend to do?
3. can I use the same 1.3V LDO to also supply DVDD or will it impact performance or some other problem?