AD9163- recommended LDO for 1.3V

I want to use the AD9163 in 1.3V mode (overclocked) to the VDDx (as described on the top of page 5)

In the datasheet the requirement is for -/+2% for this voltage.

Questions:

1. what is the load change that the LDO will see from the DAC ? I need it to select the required "load regulation" spec for my LDO. 

2. If I use the 1.3V for the serdes as mentioned, give that my FPGA's serdes is 1.2V , is this ok or will there be a problem?  if so, what do u recommend to do?

3. can I use the same 1.3V LDO to also supply DVDD or will it impact performance or some other problem?

Parents
  • ADP1761 is a good choice as LDO for the overclocking purpose.

    "1. what is the load change that the LDO will see from the DAC ? I need it to select the required "load regulation" spec for my LDO. "

    -- VDD12_CLK is the most supply that is impacted by this change. The current is Typically around 350mA but it wouldn't hurt if you count on ~400mA current draw from this rail at overclocked situation. for other supplies considering a 10% increase in the current draw will put you way in the safe side.

    "2. If I use the 1.3V for the serdes as mentioned, give that my FPGA's serdes is 1.2V , is this ok or will there be a problem?  if so, what do u recommend to do?"

    -- SERDES input is AC coupled and also the Absolute Maximum Rating of the inputs are beyond this range, so there shouldn't be a problem.

    "3. can I use the same 1.3V LDO to also supply DVDD or will it impact performance or some other problem?"

    -- based on our experiments, combining DVDD and VDD12_CLK into the same LDO degrades the phase noise performance of the DAC and we don't recommend it for new design

Reply
  • ADP1761 is a good choice as LDO for the overclocking purpose.

    "1. what is the load change that the LDO will see from the DAC ? I need it to select the required "load regulation" spec for my LDO. "

    -- VDD12_CLK is the most supply that is impacted by this change. The current is Typically around 350mA but it wouldn't hurt if you count on ~400mA current draw from this rail at overclocked situation. for other supplies considering a 10% increase in the current draw will put you way in the safe side.

    "2. If I use the 1.3V for the serdes as mentioned, give that my FPGA's serdes is 1.2V , is this ok or will there be a problem?  if so, what do u recommend to do?"

    -- SERDES input is AC coupled and also the Absolute Maximum Rating of the inputs are beyond this range, so there shouldn't be a problem.

    "3. can I use the same 1.3V LDO to also supply DVDD or will it impact performance or some other problem?"

    -- based on our experiments, combining DVDD and VDD12_CLK into the same LDO degrades the phase noise performance of the DAC and we don't recommend it for new design

Children
No Data