AD9783 temp stability

We plan to use your calibration algorithm for setting the delays to get proper alignment of the clock and the data. Your spec sheet indicates "Over temperature, the valid sampling window shifts. Therefore, when attempting operation of the device over 500 MHz, the timing must be optimized again whenever the device undergoes a temperature change of more than 20 degC." This is unclear. We thought the maximum clock rate was 500 MHz so why reference clock rates greater that 500 MHz. Plan to operate at a clock rate of 364 MHz (Interleaved data rate of 728 MSample/s) so we need to know whether a recalibration of timing is required over temperature.