AD9164 Data Structure per Lane for JESD204B

Good Morning,

I have a design that implement a JESD interface between an FPGA xilinx (using its IP: JESD204B configured in TX mode) to the DAC AD9164.

The AD9164 is configured with LMF = 811 (where I have16 bit sample; 14 bit data resolution). When I generate the transport layer data packet, I understood that with F = 1, the MSB bit (D7) of any octet must change: this means that when I configure the transport layer, the control bits of the sample cannot be both on bits 15 and 14 but I have to put a control bit on D7 (octet n) and the second one to bit D7 (octet n+1) as F=1,  and the Bit 7 of any octet must toggle.

This means that the D7 of any byte must be a toggled control bit.

The DAC AD9164 require to receive data with the following configuration (data sheet Rev C):

Lane 0 : M0S0[15:8]

Lane 1 : M0S0[7:0]

Lane 2 : M0S1[15:8]

Lane 3 : M0S1[7:0]

Lane 4 : M0S2[15:8]

Lane 5 : M0S2[7:0]

Lane 6 : M0S3[15:8]

Lane 7 : M0S3[7:0]

(where M is the single converter; S the four samples in a frame)

This DAC configuration require the 14 bits of data to be received on two lines (i.e.: Line 0: D13 – D8; Line 1: D7 – D0 with D15, D14 available for 2 controls bit).

My question is: how the DAC 9164 is expecting to receive the input data bytes?

In my case: D13 – D0 must be continuous data bits, and control bits on D14, D15 ?

With LMF = 811 I do not understand how I can implement a transport layer that support this configuration without toggle bit#7 any octet.

Could you help me ?

Many thanks in advance

mauriziob

 

  • 0
    •  Analog Employees 
    on May 30, 2018 8:38 PM

    Hello,

    The AD9164 (all ADI DACs released to date, actually) do not support "control bits" since there is typically no need for the FPGA to convey any information about the sample to the DAC.  Instead, for N=14 (14 bits converter resolution), the N'=16 (JESD204B "sample" size) is achieved by appending 2 tail bits to the LSB's of the 14-bit converter sample. So, D[15:8] = S[13:6] and D[7:0] = S[5:0],T[1:0], where S is the sample T is the tail.

    An 8 lane example is covered in the Transport layer webinar on our JESD204B page and you can also find it illustrated in figure 54 of the AD9144 data sheet.  In both cases the converter resolution is 16 instead of 14.  The only difference is that the tail bits would be inserted into the 2 lsb's of each sample (every octet on the odd numbered lanes).

    Del

  • Hi Del,

    many thanks for your reply.

    I have consider your information and now I have configured the AD9164 with LMF = 811 (where I have16 bit sample; 16 bit data resolution).

    After synchronization I have readback the following register that seem to confirm the initialization:

    Register 0x403 (SCR_L_REG) = 0x87 (scrambling enabled; 8 lines x converter)

    Register 0x404 (F_REG) = 0x00 (1 octet per frame)

    Register 0x405 (K_REG) = 0x1F (32 frames per multiframe)

    Register 0x406 (M_REG) = 0x00 (1 converter)

    Register 0x407 (CS_N_REG) = 0x0F (16 bits Converter Resolution)

    Register 0x408 (NP_REG) = 0x2F (Subclass 1; Total Number of bits x sample = 16)

    Register 0x409 (S_REG) = 0x23 (JESD204B; Number of Samples x converter = 4)

    Register 0x40A (HD_CF_REG) = 0x00 (Low Density Mode; 0 Control Word x frame)

     

    I have setup the transport layer to generate a sin wave mapped on 16 bits where only the 8 LSBs are significants and 8 MSBs are fixed to 0.

    Following the source transport layer (I have to setup a streaming length 256 bits; each line is 32 bits length: 4 frames data)

    line0_data <= "00000000000000000000000000000000";

    line1_data <= (SIN_TABLE(sin_pointer+12)(15 downto 8) & SIN_TABLE(sin_pointer+8)(15 downto 8) & SIN_TABLE(sin_pointer+4)(15 downto 8) & SIN_TABLE(sin_pointer)(15 downto 8));

    line2_data <= "00000000000000000000000000000000";

    line3_data <= (SIN_TABLE(sin_pointer+13)(15 downto 8) & SIN_TABLE(sin_pointer+9)(15 downto 8) & SIN_TABLE(sin_pointer+5)(15 downto 8) & SIN_TABLE(sin_pointer+1)(15 downto 8)); -- line0_data + x"01000000";

    line4_data <= "00000000000000000000000000000000";

    line5_data <= (SIN_TABLE(sin_pointer+14)(15 downto 8) & SIN_TABLE(sin_pointer+10)(15 downto 8) & SIN_TABLE(sin_pointer+6)(15 downto 8) & SIN_TABLE(sin_pointer+2)(15 downto 8)); -- line0_data + x"01000000";

    line6_data <= "00000000000000000000000000000000";

    line7_data <= (SIN_TABLE(sin_pointer+15)(15 downto 8) & SIN_TABLE(sin_pointer+11)(15 downto 8) & SIN_TABLE(sin_pointer+7)(15 downto 8) & SIN_TABLE(sin_pointer+3)(15 downto 8)); -- line0_data + x"01000000";

    I obtain the following sinwave:

    It seems that the AD9164 is considering samples 8 bits length; I was expecting 16 bit resolution (S=0: MSBs on line#0 and LSBs on line#1; S=1: MSBs on line#2 and LSBs on line#3; S=2: MSBs on line#4 and LSBs on line#5; S=3: MSBs on line#6 and LSBs on line#7).

    Which is wrong in my design ?

    Meny thanks for your help

    mauriziob

     

  • Good morning,

    I have also changed the High Density Mode => High Density

    Readback register 0x40A (HD_CF_REG) = 0x80 (High Density Mode; 0 Control Word x frame)

    No changes into the sinwave generation

    Regards

    mauriziob

  • 0
    •  Analog Employees 
    on Jun 6, 2018 10:22 PM

    Hello,

    If you read the data sheet carefully, you will see that registers 0x400 - 0x446 are read only registers that convey, among other things, the configuration of the JESD204 transmitter (the other end of the link).  To set the appropriate JESD204 parameters in the JESD204 receiver of theAD9164, registers 0x453 - 0x457 are used.

    Del

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:05 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin