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AD9175 DAC output problem

Category: Hardware
Product Number: AD9175

I am testing a JESD204B-based RF signal chain and observing an unexpected spectrum at the output.

My setup is as follows:

  • MPSoC generates a complex sine/cosine waveform using a DDS Compiler IP (1 MHz baseband, sysref = same jesd204b tx_coreclk) .
  • The I/Q data is transmitted via JESD204B (Mode 0, 12 Gbps) to the AD9175.
  • The AD9175 operates at a 300 MSPS input data rate (with interpolation x16 from a 4.8 GHz DAC clock).
  • The internal NCO is used to upconvert the signal to around 1 GHz.
  • The RF output is measured using a spectrum analyzer.

Expected result:

  • A clean single-sideband tone around 1 GHz ± 1 MHz.

Observed result:

  • The spectrum is spread over a wider bandwidth with a “hill-shaped” profile instead of a sharp tone.
  • There is significant spectral spreading and possible image components.
  • The signal is not a clean CW tone.

What I have already verified:

  • DDS output (I/Q) is correct.
  • JESD204B link is stable (no errors, ILAS successful).
  • SYSREF is configured as one-shot.
  • tvalid/tready handshake is stable (tready always asserted).
  • I/Q swapping does not change the result.
  • Clock sources appear stable.

Question:
What could cause this kind of spectral spreading when using complex I/Q input with the AD9175 NCO?
Could this be related to incorrect complex datapath configuration, I/Q mapping, or mixer/NCO settings inside the AD9175?

I don't really know why this result came out.

Any guidance on what to check in the AD9175 configuration would be appreciated.

  • Hi  ,

    Thank you for your interest in AD9175. Are you using the AD9175 Evaluation board? Also, could you please try the sample start-up sequence specified in Page 71 of the datasheet and let us know of your results? 

    adding   for further comments. 

    Best regards,
    Marco

  • I'm appreciated for your reply. 

    I'm using custom board, not evaluation board. The Configuration of my custom board is that the output DAC0 is connected by NCS2-222+ BALUN and outputs the RF signal as is using an SMA cable type. 

    I attach the code I programmed when setting the ad9175 registers. 

    void ad9175_init(){

    int status;

    /* START-UP SEQUENCE */
    /* 1. power-up and required Register writes */
    DAC_tx_buffer[0] = 0x00000081;//soft reset
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00000000;//release reset and set to 3-wire SPI
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00000180;//single transfer SPI
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00009100;//Power up clock receiver
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00020601;//take PHYs out of reset
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00070501;//Enable boot loader
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00009000;//Power on DACs and bias circuitry
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    sleep(1);

    /* 2. DAC_PLL Configuration */
    DAC_tx_buffer[0] = 0x00009501;//Bypass PLL
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x000790ff;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0007911f;
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    /* 3. DLL Configuraiton */
    DAC_tx_buffer[0] = 0x0000c000;//Power-up delay line
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0000db00;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0000db01;//Update DLL settings to circuitry
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0000c168;//DLL search mode
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0000c169;//DLL search mode
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0000c701;//Enable DLL read status
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    sleep(1);
    //check DLL Locked
    DAC_rx_buffer[0] = dac_read(0x0080c3FF, 0x01, 0x18, 0x08);// data rising catch, total 24 bit adresss 16 bit, data 8 bit

    /* 4. Calibration */
    DAC_tx_buffer[0] = 0x0000502A;//optimized setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00006168;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00005182;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00005183;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00008103;
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    /* 5.JESD204B Mode Setup */
    DAC_tx_buffer[0] = 0x00010000;//power up digital datapath when internal clocks are stable
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011000;//JESD mode : Single-link, Mode 0
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011182;//Interpolation / Main : x8, Channel : x2
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00008400;//AC-coupled mode
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00031200;//SYNCOUT error duration
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00030000;//single link, select Link0, disabled the links
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00047509;//soft reset the JESD204B deframer
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045300 ;//L-1 = 0 ,(bit7)Scrambling for SERDES data(SCR)(off = 0, on = 1)
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045403;//F-1 = 3
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0004551F;//K-1 = 31, Default
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045601;//M-1 = 1
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0004570F;//N-1 = 15, CS(number of control bits per sample) = 0
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0004582F;//NP-1 = 15, (bit7-5)Subclass = 1
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045920;//JESD204B, S-1 = 0
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045A80;//HD = 1, CF = 0
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045001;//DID(Device ID) = 1
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045100;//BID(Bank ID) = 0
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045200;//LID0(Lane ID) = 0
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00045D46;//Checksum

    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0004b8ff;//JESD IRQ_ENABLEA
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0004b901;//JESD IRQ_ENABLEB
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00047501;//JESD204B deframer out of reset
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0000201C;//IRQ: SYSREF jitter, DATA READY, LANE FIFO
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    DAC_rx_buffer[1] = dac_read(0x00846CFF, 0x01, 0x18, 0x08);//bit0 interlane deskew status for lane0

    /* 6. Channel DAC Datapath Setup : Digital Gain and channel NCOs */
    DAC_tx_buffer[0] = 0x00000801;//channel0_paging
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00014600;//gain_lsb[7:0] : 0dbm
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00014708;//gain_msb[11:8] : 0dbm
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00013040;//Enable NCO, disable test tone generation
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    //FTW(NO USED)
    DAC_tx_buffer[0] = 0x00013200;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00013300;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00013400;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00013500;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00013600;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00013700;
    dac_write(DAC_tx_buffer, 0x01, 0x18);


    DAC_tx_buffer[0] = 0x00013800;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00013900;
    dac_write(DAC_tx_buffer, 0x01, 0x18);


    DAC_tx_buffer[0] = 0x00013101;
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    /* 7. Main DAC Datapath Setup : PA Protect and Main NCOs */
    DAC_tx_buffer[0] = 0x00000840;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011208;//config 0
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    DAC_tx_buffer[0] = 0x00011455;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011555;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011655;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011755;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011855;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011935;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00011301;
    dac_write(DAC_tx_buffer, 0x01, 0x18);


    /* 8. JESD204B SERDES Required Interface Setup */
    DAC_tx_buffer[0] = 0x000240AA;//EQ Setting, for insertion loss <= 11dB => 0XAA
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x000241AA;//EQ Setting, for insertion loss <= 11dB => 0XAA
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00024255;//EQ Setting, for insertion loss <= 11dB => 0X55
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00024355;//EQ Setting, for insertion loss <= 11dB => 0X55
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0002441F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0002451F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0002461F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0002471F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0002481F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0002491F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00024A1F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00024B1F;//EQ Setting
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    //POWER DOWN Unused PHYs
    DAC_tx_buffer[0] = 0x000201FE;//1111 1110 ; BIXx = 0(on), BITx = 1(off)
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00020301;//SYNCOUT Driver power(Single link mode)
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00025301;//SYNCOUT0 output : LVDS
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    //Private Initailization Sequence
    DAC_tx_buffer[0] = 0x00021016;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021605;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x000212FF;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021087;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021611;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021301;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021300;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00020000;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    sleep(1); //TIME LONGER
    DAC_tx_buffer[0] = 0x00021086;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021640;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021301;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021300;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021086;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021600;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021301;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021300;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021087;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021601;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021301;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00021300;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00028005;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00028001;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    sleep(1);

    //check SERDES PLL locked
    DAC_rx_buffer[2] = dac_read(0x008281FF, 0x01, 0x18, 0x08);//BIT0 = 1 -> SERDSES PLL is locked

    /* 9. Transport Layer Setup, Synchronization, and Enable Links */
    //crossbar setup. (Default)
    DAC_tx_buffer[0] = 0x0003061C;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0003070C;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00030403;//LMFC DeLay
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00030500;
    dac_write(DAC_tx_buffer, 0x01, 0x18);


    //if operating in Subclass 1, send SYSREF pulse edges to eh device for synchronization alignment //
    DAC_tx_buffer[0] = 0x00003BF1;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00003910;//sysref_err_window
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00003A00;
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x00003A02; //one-shot ready
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    //pulse request
    hmc_resyncronize();
    usleep(50);
    DAC_rx_buffer[3] = dac_read(0x00803AFF, 0x01, 0x18, 0x08);//BIT4 = 1 -> confirm the rotation occured.

    usleep(500);

    DAC_rx_buffer[8] = dac_read(0x008302FF, 0x01, 0x18, 0x08);// Latency


    DAC_tx_buffer[0] = 0x00030001;//Enable link
    dac_write(DAC_tx_buffer, 0x01, 0x18);

    DAC_rx_buffer[1] = dac_read(0x00846CFF, 0x01, 0x18, 0x08);//bit0 interlane deskew status for lane0


    //hmc_resyncronize();

    /*Cleanup register*/
    DAC_tx_buffer[0] = 0x00008513;//SET to the default register value
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0001DE00;//Disable analog SPI. To debug and continue readback capability, wirte 0x03
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x000008C0;//Page all main DACs FOR TXEN control update
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    DAC_tx_buffer[0] = 0x0005960C;//SPI turn on TXENx feature >> SPI REG
    dac_write(DAC_tx_buffer, 0x01, 0x18);
    }

    After configuring the device and successfully completing both CGS and ILAS tests,  I measured the RF output using a spectrum analyzer.  The observed result matches the specturm shown in the attached figure from my q&a. 

    Currently, the SYSREF and device clk  are provided using the HMC7044 and ADF4377.

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