I am implementing JESD204B Mode 10 (M=1,L=1,S=1,F=2) on the AD-FMCDAQ3 with a ZCU102 carrier.
Link Configuration:
-
DAC Sample Rate (Fdac): 500 MSPS
-
Interpolation: 1x (Data Rate = 500 MHz)
-
Calculated Lane Rate: 20×500 MHz×(1/1)=10 Gbps
-
Required SerDes PLL Reference (fref): Lane Rate/40=250 MHz as per datasheet
The Problem: In the ACE Software Tool, when the DAC PLL is disabled, the tool routes the external 500 MHz clock (Fdac) directly to the SerDes PLL input. This provides a 500 MHz reference, which is 2x higher than the 250 MHz expected for a 10 Gbps link.
Technical Questions:
-
Clock Division: Does the AD9152 automatically apply a divide-by-2 prescaler (e.g., via Register 0x289) when the DAC clock is used as the SerDes reference in this mode to reach the required 250 MHz? and also kindly suggest register values for 0x291,0x296,0x28A
-
PLL Bypass Procedure: I am disabling the DAC PLL via Register 0x083. To properly bypass this block, is it sufficient to simply write the disable bit to 0x083, or must I still write all the required DAC PLL configuration registers (multipliers, VCO range, etc.) even though the block is not being used?
-
ACE Tool Accuracy: Is the ACE tool’s clock tree visualization accurate for this configuration, or is it missing an internal divider stage in its display?
