AD9154 FMC EBZ DAC PLL not being locked when configured through SPI

Hi kiriuxa ,

Hi kiriuxa ,

• Ensure the DAC is getting a proper reference clock.
  
  • The AD9154‑FMC‑EBZ normally gets its clock from the on‑board AD9516‑1, which ACE configures. If you bypass ACE and drive the FMC clock yourself, you must also configure the AD9516 or feed the clock through the J1 SMA input—otherwise the DAC may not actually receive the 200 MHz reference. 
• Confirm that the DAC clock you want is within the PLL’s valid operating range.
  
  • The DAC PLL’s VCO must stay between 6–12 GHz. The output DACCLK = VCO ÷ LODIV, so very low sample rates often cannot be generated through the PLL. In those cases, bypass the PLL and drive CLK± directly. Also ensure the CLK± signal meets the required differential swing (~0.4–2.0 Vppd) and common‑mode range.

Please see the similar EngineerZone questions below for reference:

• AD9154: DAC PLL not locking
• AD9154 SERDES PLL not locking

Thanks and kind regards,

Alex

Hi AlexAtienza ,

thank you very much for the answer. We have been already using the J1 SMA input on the AD9154‑FMC‑EBZ board to provide the cloak. The HW engineers have also confirmed that the clock signal of 200MHz can be observed on the CLK± pins.

Does ACE always configure the AD9516 clock generator by default? In our earlier tests, when we were using just ACE, without direct SPI, DAC PLL wouldnt lock until we have provided a clock signal through the J1 SMA input.

Regarding your second point, would a DAC CLK frequency of 800Mhz work on the DAC? We have been using this value for some time in ACE already, and the DAC operated correctly in all our tests.

Thank you!

Best regards,
Kiril

Hi kiriuxa ,

kiriuxa said:

Does ACE always configure the AD9516 clock generator by default?

• Yes, ACE does configure the on‑board AD9516‑1 clock generator on the AD9154‑FMC‑EBZ, so when you bypass ACE you must configure the AD9516 yourself or ensure the J1 SMA clock is properly routed through it.

kiriuxa said:

Regarding your second point, would a DAC CLK frequency of 800Mhz work on the DAC?

• A DAC clock of 800 MHz is fully supported on the AD9154, either by driving it directly (PLL bypass) or by using the DAC PLL.  And, according to Table 2 of the datasheet, the maximum DAC clock rate is 2.4 GHz, so 800 MHz is well within the valid operating range.

Thanks and kind regards,

Alex

Hi AlexAtienza ,

Sorry for the late response. I have been doing some other work on the project and did not test the SPI configuration that much.
Regarding the clock configuration through ACE. I do not think that the configuration of the on-board clock generator applies in my case. When the clock signal is not routed through J1 SMA clock connected, ACE cannot configure the evaluation DAC. Only when the clock signal is sent, both PLL locks get configured. This is an offtopic question, as I wont be using the ACE software to configure the DAC, but Iis there an option in the ACE software to enable the automatic clock configuration?

Regarding the SPI configuration: I have noticed a strange behaviour, where if the clock cable is disconnected and then connected back to J1, the PLL locks will be configured successfully with the current configuration, but after some time, the configuration will start to fail again. We believe that the problem might be with the cable that we use to send the clock signal, but this requires testing. This at least means that the data, that is being sent through SPI, is correct. I am still very confused about why this behaviour is only observed when configuring through SPI directly, as when using ACE, the PLL locks get configured every time, without disconnecting the cable. Do you perhaps have any ideas why this might be the case? I know ACE does a lot more additional writes to the DAC, but the target registers are not mentioned in the set up guide.

Thank you,
Best regards,

Kiril

Hi kiriuxa ,

Based on what you describe, the behavior strongly points to a clock‑ and timing‑related PLL startup issue, not incorrect SPI data. ACE depends on a live reference clock at J1 and will not complete PLL bring‑up unless that clock is already present, but it also performs additional sequencing, delays, and internal resets that make the process robust. In your direct SPI flow, enabling and calibrating the DAC PLL likely happens before the clock is fully stable, so the PLL calibration can fail and never retry. Hot‑plugging the clock effectively restarts the reference activity, allowing the existing configuration to lock temporarily. This difference explains why ACE locks reliably while your SPI setup is intermittent. The most effective fixes are to add a longer delay after reset before enabling the DAC PLL, explicitly disable → enable → recalibrate the PLL, and verify clock amplitude and edge quality at power‑up, especially if the cable is marginal.

Thanks and kind regards,

Alex