I have a couple questions regarding the Rev C data sheet of the AD9776a DAC. On page 28 register 3 bit 7 shows DATACLK Delay Mode. Page 30 describes this same bit as reserved set to 0. I am guessing that this bit is really the DATACLK Delay Mode bit and that it can be set to a 1 and that setting this bit to a 1 allows the part to automatically determine the data clk delay needed to satisfy the data timing margin that is set in register 3 bits [3..0]. Is that correct???
Register 3 bit 6 is shown as reserved (set to 0) on page 28. Page 30 shows bit 6 as reserved and that it should always be set to a 1 with a default of 0. I am guessing that since the default is 0 that bit 6 should always be set to a zero. What should bit 6 in register 3 be set to??
Register 2 bit 4 is the DATACLK Delay enable bit. It says on page 29 that more details on this feature are discussed in the optimizing the data input timing section but DATACLK Delay enable bit isn't mentioned at all. I assume that I should set this enable bit after I have the input reference clock set up and data is streaming to the part. Is that correct??
In digital control register 1 I see a bit called DATACLK Delay [4]. I assume that this is the most significant bit of the DATACLK Delay bits [3..0] located in register 4 bits [7..4]. Figure 86 on page 48 shows that DATACLK Delay bits [3..0] is only 4 bits. Is DATACLK Delay a 5 bit number??
The data sheet also states on page 48
One error check operation
is performed per device configuration. Any change to the Data
Timing Margin[3:0] or DATACLK Delay[3:0] values triggers a
new error check operation.
if I set bit 7 of register 3 to a 1 (DATACLK Delay Mode = 1) Is the timing margin constantly checked and is the DATACLK Delay constantly updated?
Thanks
