Hi all,
I've spotted a couple of AD9161/AD9162 datasheet mistakes while tracking down a separate issue and wanted to document them here for others.
1) Page 49, section Clock and Data Recovery
"After configuring the CDR circuit, reset it and then release the reset by writing 1 and then 0 to Register 0x206, Bit 0"
This implies the reset is active high. This is in contradiction to Table 43, the registers on pg. 201, and my own testing, all of which which indicate the reset bit is active low.
2) Page 71, section Datapath PRBS
"Write Register 0x14, Bit 2 = 0 for PRBS7 or 1 for PRBS15"
The correct register is 0x14B not 0x14.
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As a side note, the issue I am currently facing is no data out of the datapath. The DAC reports everything is good, PLL locked, CGS/ILAS present, link status all good, no bit errors. The only signs of an issue are the JRX_DATA_READY IRQ is set and the SNAPSHOT reg reads all 0's. This link is one lane and passes all three PRBS tests with no I or Q errors. I have closely followed the setup procedures in tables 42-44. Link parameters look fine. Does anyone have recommendations of what could be the issue?
Many thanks
