AD9744-FMC-EBZ-J3/J4 EXT REF/DAC CLK

Hi S1640 ,

Thank you for forwarding the customer’s queries to us.

Using a low-frequency clock in the 100 kHz–500 kHz range is technically possible with the AD9744 IC but requires hardware modifications (removal of RF transformer and proper coupling), and software/FPGA validation to ensure the evaluation ecosystem doesn’t reject or alter the low clock input.

Could you please share more details about the customer’s requirements or applications so we can evaluate other possible alternatives? Additionally, could you clarify why they selected the AD9744 for their application?

Please find below additional details regarding your queries

S1640 said:

What is the supported frequency range for the external clock input?

• From practical standpoint DAC can handle DC to 210 MSPS; however, we usually recommend getting a DAC with a sampling rate (F_CLK) at least 4x the desired F_OUT.

S1640 said:

The external clock input is equipped with an RF transformer (TMC2-43X+), so it is unlikely that frequencies below 10 MHz can be input. So, I think that modifications such as removing the RF transformer will be necessary. Are there any other functional issues?

• You’re correct — the TCM2‑43X+ restricts operation below 10 MHz.
• Remove transformer, add buffer and coupling; verify CMOS thresholds.
  • You can refer to "Figure 51. LFCSP Evaluation Board Schematic—Clock Input" of RevC datasheet.

S1640 said:

Even if a clock compatible with the electrical characteristics of the AD9744 and the Spartan 6 on the SDP-H1 are input, I am concerned that there may be frequency limitations due to the SDP-H1, ACE software, DPG Lite software, or other design tools, which is why I would be confirmed this question.

• SDP-H1 is optimized for evaluating high-speed DACs, typically in the tens to hundreds of MSPS range.  As per our performed evaluation, it can support down to 10MHz only.  At present, we do not have a controller capable of operating at very low data rates due to limitations in both hardware and software architecture.
• ACE & DPG Lite software can support low-frequency clock.

Thanks and kind regards,

Alex

Hello Alex-san,
Thank you for your quick response.
I haven't received a response regarding the customer's application yet, so I will send you a message once I receive one or if there is any further confirmation. First of all, thank you for your quick response.

Hello Alex-san,
Thank you for your quick response.
I haven't received a response regarding the customer's application yet, so I will send you a message once I receive one or if there is any further confirmation. First of all, thank you for your quick response.