repeater

Hi dhjung ,

Thank you for using AD9148. We'll look into this and provide you a response as soon as possible.

Regards,
Zaeefa

Hi dhjung ,

Are you using the AD9148 Evaluation Board or a custom board with the AD9148? If the latter, can you please provide a schematic of your board? 

The AD9148 is supposed to work at an operating temperature of -40-to-85 degrees Celsius. There might be a different component either in the CLK input, the digital data input, or the output datapath of AD9148 that's not rated for 65 degrees or higher. 

Best regards,
Marco

PDF

First of all, thank you for your response.
When the temperature rises, the output stops, but if I re-initialize the register settings, it returns to normal. From the symptoms, it looks as if the registers were reset. The datasheet says the TAP interface should be connected to DVSS, but I left it floating. I’m wondering if leaving it floating could be causing the issue. The clock is from si5386a-e-gm.(-40~+85), data line connect to xcku3p (-40~+100)

I have a few questions regarding the device operation described in the datasheet. Could you please help clarify the following items?

1. On page 7, the datasheet specifies a “Power-Up Time = 100 ms.” Does this mean that we must wait 100 ms after power is applied before performing any register configuration?

2. On page 13, the RESET pin description states “pull up to IOVDD.” Does this indicate that the RESET pin has an internal pull-up to IOVDD?

3. On page 68, the start-up sequence includes the step “issue a hardware reset (optional).” Does this mean that issuing a hardware reset after power-up is not strictly required?

4. After releasing the RESET pin, is there any required delay before beginning register configuration?

Thank you very much for your support.

Hi dhjung ,

Please see below details addressing your initial concerns.

dhjung said:

I also had the TMS TDI TCK TDO pin float on the circuit diagram and I was wondering if this is related.

dhjung said:

From the symptoms, it looks as if the registers were reset. The datasheet says the TAP interface should be connected to DVSS, but I left it floating. I’m wondering if leaving it floating could be causing the issue.

• Similar to most IEEE‑1149.1 TAP implementations, TCK, TMS, and TDI must not be left floating. Noise or leakage can inadvertently clock the TAP controller, causing state transitions that may place the device into Test‑Logic‑Reset or other test modes, potentially disrupting normal operation. As indicated in Table 10 of the RevB datasheet, it is recommended to tie the TAP pins to DVSS when JTAG is not in use. Floating pins at elevated temperatures can increase leakage and susceptibility to crosstalk, making unintended TAP activity more likely.
  
  
  • If you do not plan to use JTAG on the AD9148, tie TMS, TDI, TCK, TDO to DVSS at the device (short traces, no dangling stubs). If you want future access, use strong pulldowns (e.g., 1 k–10 k to DVSS) on TCK/TMS/TDI and keep TDO high‑Z; add a 0 Ω link to lift them during debug. This matches common best practice for unused TAPs.
  • Add 10 kohm pulldowns on TMS, TDI, TCK to DVSS (and keep TDO floating or tied per datasheet recommendation). Re‑run the chamber test. If the issue disappears, the culprit was floating TAP.

dhjung said:

The clock is from si5386a-e-gm.(-40~+85), data line connect to xcku3p (-40~+100)

• Si5386A‑E‑GM
  • Confirm there’s no loss‑of‑lock (LOL) or reset timing during thermal transitions.  If the AD9148 loses its input clock, mode changes or internal PLL behavior could also disrupt the output.
• XCKU3P (Kintex UltraScale+)
  • Verify that IO bank voltage references and LVDS drive remain stable across temperature, and that your FPGA doesn’t tri‑state or reset I/O on configuration reloads.

Alternative system/board isolation:

• To isolate a specific device in your system or board, focus on the target component suspected of causing issues during high-temperature testing. Refer to the sample illustration below for guidance.

Thanks and kind regards,

Alex

Hi dhjung ,

1. You're correct. The power-up time is the time it takes for the DAC core to power-up and make the device fully operational. This time must be finished before writing to the DAC. 
2. No, the RESET pin must be externally pulled up to IOVDD (Input-output supply) through a pull-up resistor (or tied directly to IOVDD if you don't plan to use hardware reset). This pin is active-low, thus puling it high (to IOVDD) keeps the device out of reset. You may refer to the schematic of the AD9148 Evaluation Board for reference on connecting the RESET pin. 
3. Yes, a hardware reset is not strictly required, although it is recommended to provide a hardware reset to the DAC upon power-up for robustness in ensuring the registers are set back to default. If a hardware reset is not provided, complete the power-up time (to let the internal clocks, circuits, and blocks stabilize) then provide a software reset to the DAC before configuring it for operation. 
4. This delay is already incorporated during the power-up time of 100ms. After device power-up and de-asserting RESET, the DAC bias circuits, internal logic, and PLL (if enabled) are stabilizing. I recommend following the startup sequence stated in page 68. 

Best regards,
Marco

Hi. JMMina.

I have an additional question regarding point 2.

In the EVM schematic, the RESET (H3) pin is connected only to a switch. There is no pull-up resistor.

On page 59 of the datasheet, it specifies a 10 kΩ pull-down resistor for RESET(Was ‘I120’ incorrectly labeled?). I would like to request additional clarification on this.

Best Regards,

dhjung

Hello,

The RSET shown in figure 77 refers to the 10 kohm resistor that is used used to set the "bias current" used for the DAC cores.

As stated previously.................make sure that you use a pull-up resistor (10 K) on the RESET "digital" input so that it remains high if the digital device driving this pin becomes accidently "tri-stated" and unable to keep this pin HIGH after having initially issued a RESET pulse during power-up initialization.