Output waveform is distorted

Hi sru853 ,

Thank you for your interest in AD9747. AlexAtienza will look into this query and get back to you as soon as possible.

Are you using the AD9747 Evaluation Board? If not, can you please provide your schematic? Also, where are you getting the DACCLK from and what FPGA board are you using? 

Best regards,
Marco

Hi Marco,

Thanks for the reply. 

I’m working on a fully custom board where the DACCLK for the AD9747 is being generated by an LMK04828 clock generator. The FPGA used in the design is a Zynq MPSoC.

Here is the schematic of AD9747. 

Thanks & Regards,

Srujan 

Hi sru853 ,

Do you have a frequency domain capture? It would be best to see which frequencies are showing at the output causing the waveform to be distorted. Kindly check if there are ripple noise from the supply rails and noise coming from the clock pins. 

Best regards,
Marco

Hi sru853 ,

Additionally, could you please confirm the values of R30, R31, R36, and R37 (RLOADs)? Based on the schematic diagram you provided, they appear to be 50 kΩ. However, the EVB schematic shows 49.9 Ω resistors installed, which you may follow for consistency.

Regarding the distorted output that worsens with increasing DCO frequency, please try reconfiguring the DAC after changing the DCO frequency, or perform a power cycle on your setup to see if that resolves the issue.

Thanks and kind regards,

Alex

Hi Alex,

The Resistor values are 50 ohm. Not 50k ohm. 

It looks heavily distorted when I view in spectrum analyser. 

Hi Marco,

Here I'm attaching the video. 

Signal Frequency = 50MHz

Sampling Frequency = 200 MHz 

Thanks & Regards,

Srujan Vedula 

Hi sru853 ,

Apologies for the delayed response.  If this issue is not yet resolved, you can check below items on your setup.

• Output Stage
  • Just to ensure correct orientation or pin connections of the baluns, please help to follow the EVB schematic diagram.

• Clock Integrity
  • Verify LMK04828 configuration: low jitter mode, proper PLL loop bandwidth.
  • Clock distribution as per Table 5 of rev C datasheet.

Thanks and kind regards,

Alex

Hi sru853 ,

The output does look to be heavily distorted, could you try lowering the output frequency and see if there's a range where there's no distortion? Try around <10MHz. 

As suggested by Alex, you might want to check the clock input (LMK04828) and see if it's noisy. Are you using the default register values? If both are checked, the problem might be the timing of data transfer from your FPGA to the DAC (refer to Page 25 of Rev C datasheet). There isn't any issues with the schematic you sent, but you could the AD9747 Evaluation Board as reference for your design.

Best regards,
Marco

Hi Marco,

Sorry for the late reply. 

Right now I do not have the board to test but could you please clarify if any reconstruction filter required after DAC to smooth the waveform?

Thanks & Regards,

Srujan