| SLA Status | Assignee | Support Status |
|---|---|---|
| SLA Closed. Met after 43 hours |
lloben AlexAtienza JMMina |
Closed |
AD9776A
Production
The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit, high dynamic range digital-to-analog converters (DACs) that provide a sample rate of 1 GSPS, permitting...
Datasheet
AD9776A on Analog.com
Hello,
I have a design that includes the AD9776A. Ref clock is driven by an LVDS driver chip. The output of the LVDS driver chip is ac coupled and then driven into a pair of 50 ohm resistors as figure 73 in the data sheet shows. I am confused by the DAC CLOCK INPUT (REFCLK+, REFCLK−) specification on page 6 of the data sheet. The DAC CLOCK INPUT (REFCLK+, REFCLK−) specification says the minimum differential peak to peak voltage is 400 mV, typical is 800 mV and max is 2000 mv.
The specification for LVDS is min 200 mV, typical 350 mV and max is 450 mV. The typical differential voltage for LVDS is 350 mV which is below the minimum differential voltage of the AD9776A. It seems like sourcing the REF Clock using an LVDS driver may fail if the LVDS driver is providing a typical voltage of 350 mV or even worst if the driver shades more towards the minimum. Am I interpreting the number incorrectly?
Would it make more sense to use two 60 ohm resistors instead of two 50 ohm resistors as shown in figure 73? This would bring the typical differential voltage to 420 mV (assuming the LVDS driver sources 3.5 mAmps).
It seems as though the differential voltage specification and the recommendation of using an LVDS driver are not compatible. Can you address this issue?
Thanks
Hi Bill.AvidSystems ,
Thank you for using AD9776A.
You are correct regarding the compatibility between the AD9776A's REFCLK input requirements and the voltage levels typically provided by standard LVDS levels. This is actually noted on page 42 of the Rev. C datasheet under the section 'DRIVING THE REFCLK INPUT,' as shown below. While this termination method is standard for LVDS, it serves only to match impedance and does not increase the signal amplitude. That’s why it might seem puzzling at first, but the datasheet recommends using an LVDS driver.
To drive the REFCLK, please refer on application note below. It reinforces the idea that LVDS is suitable for clock distribution, but termination and signal swing must be carefully managed to meet specific device requirements like those of the AD9776A.
AN-1177: LVDS and M-LVDS Circuit Implementation Guide
Thanks and kind regards,
Alex
