Hi,
I am using a Kintex-7 FPGA (not KCU105) to evaluate the AD9174-FMC-EBZ. I am facing some difficulty in understanding which IO standard is appropriate to use for interfacing the SYSREF signal with my FPGA, generated from the HMC7044.
Looking at the schematic provided by ADI, we see that SYSREF_2 (p/n) from SCLKOUT13 (+/-) are the relevant nets, which are ac-coupled. When using the ACE Macro, it is shown that register 0x0152 has 3 (=0x03) written to it. This corresponds to CML mode, which has a diff. swing of ~1400/2000 mVpp based on power mode. I was confused about how to interface such a signal from the LA bus of the FMC Connector, as this is well beyond the LVDS spec?
Thanks very much in advance, and please let me know if I have misunderstood something here - I have considered the fact that perhaps the ACE Macro is 0x30 (the default value for 0x0152), however this seems inconsistent with other entries in the table (as there are entries like 0x60, etc.). If this is the case, please let me know.
Attaching relevant screenshots.
Thank you very much for your time!
