Freq Switching time

Hi sarojini 

Thank you for your interest in AD9163. Kindly give zpandangan and MohammedHossain some time to look into this issue and get back to you.

Best regards,
Marco

Hi Sarojini,

sarojini , zpandangan , MohammedHossain 

It's been more than 3weeks. No one has replied for my query.

AD916x-

FTW update rate depends on SPI speed. For 100 MHz SPI we have 10 nS /cycle and it requires 24 cycles of SPI instruction for AD9164. Which is equivalent to 240ns. 2 additional cycles of overhead may be required for a SPI write  

JESD 204B Lane rate-

Lane rate = (M × N' × [10⁄8] × Fs) ∕ L

where: M is the number of converters on the link.

 N' is the number of informational bits sent in a sample (including sample resolution, control and tail bits).

Fs is the device or sample clock. L is the lane count.

Lane rate is the bit rate for a single lane. 10⁄8 is the link overhead due to 8b⁄10b encoding.

JESD204B standard supports a maximum lane rate of 12.5 Gbps per channel.

Hi Mohammed Hossain,

Thanks for the reply.

We are using AD9174.

I understood the FTW calculation.

1. May I know the switching time of it from one frequency to another frequency.

2. Does AD9174 takes QPSK Modulated data and mix the I & Q then gives the output?

Thanks & Regards,

C Ashok Reddy