JESD is not able to pass DATA section.

Hello,

I am trying to use only one DAC output and a single channel interface on the AD9173. I’ve gone through the datasheet and configured the JESD mode accordingly using the AD917x API. However, the JESD link consistently gets stuck in the CGS (Code Group Synchronization) phase, and I’m not sure what I’m missing.

Could you please help me understand how to properly configure the JESD mode for this setup using the API?

Config Codes:

#ifndef APP_CONFIG_3_H_
#define APP_CONFIG_3_H_

#include "hmc7044.h"
#include "ad9172.h"
#include "axi_adxcvr.h"
#include "axi_jesd204_tx.h"
#include "axi_dac_core.h"
#include "parameters.h"
#include "inttypes.h"
#include "no_os_error.h"
#include <xparameters.h>
#include <xil_cache.h>
#include "no_os_spi.h"
#include "spi_extra.h"
#include "no_os_gpio.h"
#include "gpio_extra.h"

static struct xil_spi_init_param xil_spi_param = {
.type = SPI_PS,
.flags = 0
};

static struct no_os_spi_init_param hmc7044_spi_param = {
.device_id = SPI_DEVICE_ID,
.max_speed_hz = 10000000,
.mode = NO_OS_SPI_MODE_0,
.chip_select = SPI_HMC7044_CS,
.platform_ops = &xil_spi_ops,
.extra = &xil_spi_param
};

static struct hmc7044_chan_spec chan_spec[4] = {
{.disable = 0, .num = 2, .divider = 8, .driver_mode = 1}, /* DAC_CLK */
{.disable = 0, .num = 3, .divider = 512, .driver_mode = 1}, /* DAC_SYSREF */
{.disable = 0, .num = 12, .divider = 8, .driver_mode = 2}, /* FPGA_CLK */
{.disable = 0, .num = 13, .divider = 512, .driver_mode = 2}, /* FPGA_SYSREF */
};

static struct hmc7044_init_param hmc7044_param = {
.spi_init = &hmc7044_spi_param,
.clkin_freq = {122880000, 0, 0, 0},
.vcxo_freq = 122880000,
.pll2_freq = 2949120000,
.pll1_loop_bw = 200,
.sysref_timer_div = 1024,
.pulse_gen_mode = 0,
.in_buf_mode = {0x15, 0, 0, 0, 0x15},
.gpi_ctrl = {0x00, 0x00, 0x00, 0x00},
.gpo_ctrl = {0x1f, 0x2b, 0x00, 0x00},
.num_channels = 4,
.channels = chan_spec,
};

static struct jesd204_tx_init tx_jesd_init = {
.name = "tx_jesd",
.base = TX_JESD_BASEADDR,
.octets_per_frame = 2,
.frames_per_multiframe = 32,
.converters_per_device = 2,
.converter_resolution = 16,
.bits_per_sample = 16,
.high_density = false,
.control_bits_per_sample = 0,
.subclass = 1,
.device_clk_khz = 184320, /* (lane_clk_khz / 40) */
.lane_clk_khz = 7372800, /* LaneRate = ( M/L)*NP*(10/8)*DataRate */
};

static struct adxcvr_init tx_adxcvr_init = {
.name = "tx_adxcvr",
.base = TX_XCVR_BASEADDR,
.sys_clk_sel = ADXCVR_SYS_CLK_QPLL0,
.out_clk_sel = ADXCVR_REFCLK_DIV2,
.lpm_enable = 1,
.lane_rate_khz = 7372800, /* LaneRate = ( M/L)*NP*(10/8)*DataRate */
.ref_rate_khz = 368640, /* FPGA_CLK, output 12 of HMC 7044 */
};

static struct no_os_spi_init_param ad9172_spi_param = {
.max_speed_hz = 1000000,
.mode = NO_OS_SPI_MODE_0,
.chip_select = SPI_AD9172_CS,
.platform_ops = &xil_spi_ops,
.extra = &xil_spi_param
};

static struct xil_gpio_init_param xilinx_gpio_init_param = {
.type = GPIO_PS,
.device_id = GPIO_DEVICE_ID
};
static struct ad9172_init_param ad9172_param = {
.spi_init = &ad9172_spi_param, /* no_os_spi_init_param */
.gpio_reset = {
.number = 54 + 0,
.platform_ops = &xil_gpio_ops,
.extra = &xilinx_gpio_init_param
},
.gpio_txen0 = {
.number = 54 + 22,
.platform_ops = &xil_gpio_ops,
.extra = &xilinx_gpio_init_param
},
.gpio_txen1 = {
.number = 54 + 23,
.platform_ops = &xil_gpio_ops,
.extra = &xilinx_gpio_init_param
},
.dac_rate_khz = 11796480, /* or sample rate */
.dac_clkin_Hz = 368640000, /* DAC_CLK, output 2 of HMC 7044 */
.jesd_link_mode = 2,
.jesd_subclass = 1,
.dac_interpolation = 8,
.channel_interpolation = 4,
.clock_output_config = 4,
.syncoutb_type = SIGNAL_LVDS,
.sysref_coupling = COUPLING_AC,
};

static struct axi_dac_init tx_dac_init = {
"tx_dac",
TX_CORE_BASEADDR,
4,
NULL
};

#endif /* APP_CONFIG_3_H_ */